Multi-Level PIC Die Structure for Shorter Substrate Bump Coupling
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in reducing the distance between photonics integrated circuit (PIC) bumps and substrate bumps, leading to increased power efficiency losses and mechanical stress on sensitive components due to deep cavities and sloping edges, which affect bonding and fiber alignment.
Innovation Solution
The implementation of a PIC die with a thick portion and a thin portion, where the thin portion overhangs to reduce the distance between electrical contacts, using a transition structure to support mechanical stress and facilitate direct fiber attachment, thereby reducing the substrate bump to PIC bump distance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a deep cavity substrate is used to house the PIC die, then the PIC can be positioned within the substrate, but the distance between PIC bumps and substrate bumps increases leading to power efficiency losses
Solution Approach 1:
The PIC die is designed with a multi-level structure where portions of the die extend beyond the substrate plane in both upward and downward directions. This vertical dimensionality allows electrical contacts to be positioned closer together, reducing the bump distance from what would otherwise be a larger horizontal separation, thereby improving power efficiency.
Solution Approach 2:
The PIC die is segmented into multiple levels with different thicknesses. A first portion of the die extends above the substrate top surface while a second portion extends below it. This segmentation allows different regions of the die to serve different functions and positions electrical contacts optimally for minimal bump distance.
2Reliability
If a deep cavity substrate is used to house the PIC die, then the PIC can be positioned within the substrate, but mechanical stress is placed on sensitive components affecting bonding and fiber alignment
Solution Approach 1:
Different portions of the PIC die have different thicknesses tailored to their specific functions. The transition between thick and thin regions is designed to manage stress distribution. Sensitive components are positioned in regions with appropriate thickness to minimize mechanical stress while maintaining structural integrity for reliable bonding and fiber alignment.
Solution Approach 2:
By extending portions of the die both above and below the substrate plane, the structure creates a more favorable stress distribution pattern. The multi-level configuration allows stress to be distributed across different vertical levels rather than concentrated in a single plane, protecting sensitive components.
3Loss of energy
If the PIC die is made thinner to reduce bump distance, then electrical conductivity improves, but mechanical strength decreases making the die more vulnerable to stress
Solution Approach 1:
The die employs non-uniform thickness distribution where different regions have different thicknesses optimized for their specific requirements. Regions requiring high electrical conductivity are made thinner, while regions requiring mechanical strength are made thicker. This local differentiation resolves the contradiction between conductivity and strength.
Solution Approach 2:
The die is divided into multiple segments with varying thicknesses. This segmentation allows the structure to simultaneously achieve high electrical conductivity in thin regions and high mechanical strength in thick regions, eliminating the need to choose between the two opposing requirements.
Data Source
AI summary
Embodiments described herein may be related to apparatuses, processes, and techniques related to multilevel dies, in particular to photonics integrated circuit dies with a thick portion and a thin portion, where the thick portion is placed within a cavity in a substrate and the thin portion serves as an overhang to physically couple with the substrate, to reduce a distance between electrical contacts on the thin portion of the die and electrical contacts on the substrate. Other embodiments may be described and/or claimed.