Multi-Loop Digital PLL Clocking for Accurate Phase Locking
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Solution Overview
Problem
Digital phase locked loop (DPLL) circuits face challenges in achieving accurate phase locking and minimizing noise in high-frequency clock signals due to metastability and variations in time-to-digital converter (TDC) measurements, which affect their performance and integration in compact, low-power digital circuits for mobile devices.
Innovation Solution
The implementation of multiple digital feedback loops with a time-to-digital converter (TDC) and a digitally controlled oscillator (DCO) that includes calibration techniques for TDC parameters and a supervisor circuit to mitigate metastability, ensuring accurate phase locking and noise reduction in the generated high-frequency clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single digital feedback loop is used in DPLL circuits, then the circuit complexity is reduced, but phase locking accuracy and noise immunity deteriorate due to metastability and TDC measurement variations
Solution Approach 1:
The patent divides the single feedback loop into multiple digital feedback loops (first and second digital feedback loops). The first loop handles phase error detection using TDC, while the second loop handles frequency error detection and correction. This segmentation allows each loop to specialize in specific error types, improving overall phase locking accuracy and noise immunity without requiring a single overly complex loop.
Solution Approach 2:
The patent introduces a supervisor circuit as an intermediary component that coordinates between the two feedback loops. The supervisor circuit receives outputs from both loops, determines which loop has higher priority based on error magnitudes, and selectively enables相应的 feedback paths. This intermediary structure allows the system to dynamically switch between loops, improving accuracy while maintaining manageable complexity.
2Reliability
If multiple digital feedback loops are implemented to improve phase locking accuracy, then noise immunity and phase locking performance improve, but device complexity increases
Solution Approach 1:
The patent implements two distinct feedback loops where the first loop provides phase error feedback through TDC and the second loop provides frequency error feedback. Each loop independently monitors its specific error type and feeds corrections back to the DCO. This dual feedback mechanism improves noise immunity by addressing both phase and frequency deviations, while the modular feedback structure keeps complexity manageable through clear functional separation.
Solution Approach 2:
The patent changes the operational parameters of the feedback loops by introducing priority-based enable signals. The supervisor circuit dynamically adjusts which feedback loop is active based on the magnitude of errors detected. When phase error exceeds a threshold, the first loop is enabled; when frequency error is significant, the second loop takes priority. This dynamic parameter adjustment allows the system to adapt to different operating conditions, improving reliability without requiring both loops to operate simultaneously at full complexity.
3Measurement precision
If calibration techniques for TDC parameters are added to reduce measurement variations, then phase locking accuracy improves, but power consumption and circuit complexity increase
Solution Approach 1:
The patent implements calibration techniques that perform TDC parameter calibration in advance during manufacturing or initialization phases. By pre-calibrating TDC measurement variations and storing correction parameters, the system eliminates the need for continuous real-time calibration during operation. This preliminary action significantly improves TDC measurement accuracy while keeping power consumption low during normal DPLL operation, as the calibration data is simply applied without requiring active calibration circuits to be continuously powered.
Data Source
AI summary
Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.