Multi-Metal CMOS Gate Stacks for Lower RC Delay in 3D NAND
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Solution Overview
Problem
Current memory devices face challenges in increasing memory capacity while minimizing circuit area and enhancing operational speed, particularly in 3D NAND memory arrays, where the thickness of gate electrodes like tungsten silicide limits performance due to high resistance and capacitance, leading to RC delay issues.
Innovation Solution
Implementing a multi-metal stack gate electrode with a bilayer structure of titanium nitride and tungsten nitride, which reduces the thickness to half or less than tungsten silicide while maintaining thermal stability and lower sheet resistance, thereby reducing RC delay and enhancing operational speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick gate electrode like WSiX is used, then thermal stability during fabrication is improved, but RC delay increases and operational speed deteriorates
Solution Approach 1:
The patent applies composite materials by replacing the single-material WSiX gate electrode with a multi-layer metal stack consisting of different metal layers (e.g., tungsten, tungsten nitride, titanium nitride). Each layer contributes different properties: some layers provide thermal stability during fabrication while others provide low resistance and controlled thickness, thereby reducing RC delay. This composite structure resolves the contradiction by combining materials with complementary characteristics rather than relying on a single material to satisfy both thermal stability and speed requirements.
2Speed
If gate electrode thickness is reduced, then RC delay is reduced and operational speed is improved, but manufacturing complexity increases due to difficulty in thinning
Solution Approach 1:
The patent segments the gate electrode into multiple discrete metal layers, each with controlled thickness. Instead of attempting to thin a single thick gate electrode material, the structure divides the total thickness into several thinner layers (e.g., 50-200 nm per layer), which are easier to deposit and control individually. This segmentation approach reduces the manufacturing difficulty of achieving thin overall thickness while maintaining the benefits of reduced RC delay.
3Quantity of substance
If memory density is increased, then storage capacity is improved, but circuit area increases
Solution Approach 1:
The patent changes the electrical parameters of the gate electrode by using a multi-layer metal stack with specific resistance and thickness characteristics. This enables smaller transistor dimensions and reduced RC delay, which allows for higher memory density to be achieved within the same circuit area. The parameter changes in the gate electrode material directly enable more efficient use of available area, increasing storage capacity without proportionally increasing circuit area.
Data Source
AI summary
A variety of applications can include apparatus having a memory device structured with an array of memory cells and a complementary metal-oxide-semiconductor (CMOS) device coupled to the array. The CMOS device can include a gate electrode on and contacting the polysilicon gates of a p-channel metal-oxide-semiconductor (PMOS) transistor and a n-channel metal-oxide-semiconductor (NMOS) transistor of the CMOS device, where the gate electrode is a multi-metal stack. The multi-metal stack of the gate electrode can be two levels of different metal compositions.