Multi-Metal Gate Via Structure for Void-Free Nanosheet FET Contacts
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Solution Overview
Problem
In advanced semiconductor technology nodes, dimension scaling poses challenges in forming contacts and vias to gate, source, and drain electrodes of field-effect transistors, leading to voids in gate vias and degraded contact resistance due to the use of different metal materials for metallization.
Innovation Solution
An efficient metal gap fill method is implemented using two different metal liners and bulk fill metal for improved gate via fill quality, and the same metal material is used for source/drain vias and metallization to minimize contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dimension scaling is pursued to increase functional density, then production efficiency improves and costs decrease, but manufacturing complexity increases and voids form in gate vias
Solution Approach 1:
The gate via structure is segmented into multiple metal layers (first metal layer, second metal layer, third metal layer) with different materials and functions. Each layer addresses specific requirements: the first metal layer provides adhesion and barrier functions, the second metal layer provides conductive fill, and the third metal layer provides additional conductive pathways. This segmentation allows each layer to be optimized independently, eliminating voids while maintaining manufacturing feasibility at scaled dimensions.
Solution Approach 2:
The patent employs composite material structures in the gate via, combining multiple metal materials (e.g., tungsten, copper, cobalt) with different physical and electrical properties. This composite approach allows optimization of each material for its specific function: adhesion, conductivity, or barrier properties, thereby achieving complete via fill without voids while maintaining electrical performance at scaled dimensions.
2Reliability
If different metal materials are used for metallization to optimize individual contact properties, then specific contact resistance improves, but overall contact resistance degrades due to material interfaces
Solution Approach 1:
The patent applies local quality by assigning different metal materials to specific regions and functions within the metallization structure. For example, tungsten is used in regions requiring high mechanical strength and adhesion, while copper or cobalt is used in regions requiring low electrical resistance. Each material is locally optimized for its specific function, and the multi-layer structure manages interfaces to minimize overall contact resistance while maintaining structural integrity.
3Volume of moving object
If gate via dimensions are reduced to enable further scaling, then device density increases, but void formation becomes more prevalent
Solution Approach 1:
The patent employs preliminary action by forming a seed layer or barrier layer before depositing the main conductive fill material. This preliminary layer is deposited with controlled thickness and properties to ensure complete wetting and adhesion to the via walls, preventing void formation during subsequent fill processes. The preliminary layer is specifically engineered to address potential fill issues before they occur, enabling complete via fill at reduced dimensions.
Solution Approach 2:
The patent utilizes parameter changes by adjusting deposition parameters, material composition, and layer thicknesses to optimize via fill at scaled dimensions. By changing parameters such as deposition temperature, material purity, and layer thickness ratios, the process achieves complete via fill without voids even as via dimensions are reduced, maintaining manufacturing precision throughout the scaling process.
Data Source
AI summary
A device includes a substrate, a gate structure wrapping around a vertical stack of nanostructure semiconductor channels, and a source/drain abutting the vertical stack and in contact with the nanostructure semiconductor channels. The device includes a gate via in contact with the first gate structure. The gate via includes a metal liner layer having a first flowability, and a metal fill layer having a second flowability higher than the first flowability.