Multi-mode Combined Rotator for 32-bit and 64-bit Data Alignment
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Solution Overview
Problem
As processor geometric dimensions decrease, the increasing cross-capacitance effects lead to higher power consumption and noise on chips, causing propagation delays and inefficiencies in data rotation, particularly when handling both 32-bit and 64-bit operands, as existing solutions either consume excessive on-die real estate or introduce additional delays.
Innovation Solution
A processor with a single rotator configured to support multiple modes, using a mask to adjust bit positions during rotation operations, allowing for efficient rotation of both 32-bit and 64-bit operands by generating masks to indicate special treatment for most-significant bits during right or left rotations, thereby optimizing data alignment without additional delays or real estate consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If both a 32-bit rotator and a 64-bit rotator are included within the execution core, then the processor can support both 32-bit and 64-bit rotations, but the on-die real estate increases and additional delay is introduced by adding a 2:1 mux to the critical path
Solution Approach 1:
The patent implements a single rotator unit that can perform both 32-bit and 64-bit rotation operations by detecting the operand size and configuring the rotator accordingly. The rotator uses a mask register and control logic to adapt its behavior based on whether it is processing 32-bit or 64-bit operands, eliminating the need for separate rotators for different operand sizes.
Solution Approach 2:
The patent merges the functionality of separate 32-bit and 64-bit rotators into a single unified rotator unit. By combining these functions, the design reduces the number of components, decreases on-die real estate, and removes the need for additional multiplexers in the critical path while maintaining the ability to handle both operand sizes.
2Adaptability or versatility
If the processor detects a 32-bit rotate and duplicates the 32-bit rotate data inputs to both the higher order and lower order 32 bits of the 64-bit rotator, then the processor can support both operand sizes, but the data input load increases and the speed of the rotation is reduced
Solution Approach 1:
The rotator employs dynamic configuration based on the detected operand size. When a 32-bit rotation is detected, the rotator is configured to process only the lower 32 bits, avoiding unnecessary duplication of data inputs to the higher order bits. This dynamic adaptation allows the system to maintain high rotation speed while supporting both 32-bit and 64-bit operations.
Solution Approach 2:
Instead of always duplicating data inputs to both higher and lower order bits regardless of operand size, the patent applies partial action by only duplicating when necessary for 64-bit operations. For 32-bit operations, the rotator processes only the required lower 32 bits, reducing the data input load and maintaining optimal rotation speed.
Data Source
AI summary
A system and method for efficiently rotating data in a processor for multiple operand sizes. A processor comprises a rotator configured to support multiple operand sizes. The rotator receives a rotate amount and an input operand with a size less than a maximum operand size supported by the processor. The rotator generates a mask with a same size as the received input operand. The mask comprises a number of asserted most-significant bits equal to the rotate amount. The remaining bits in the mask are deasserted. For a given rotation result bit position with an associated asserted mask bit, the rotator selects a value in the input operand at a bit position with a distance from the given result bit position equal to the rotate amount plus a difference between the maximum operand size supported by the processor and the input operand size.