Multi-Output Frequency Synthesizer with Independent PLL Clock Correction
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Solution Overview
Problem
Modern communications devices face performance impairments due to shared reference clock frequency variations caused by Automatic Frequency Control (AFC) adjustments, which affect multiple communication blocks differently, leading to instability and disruptions in clock accuracy requirements across various functions.
Innovation Solution
The method involves generating multiple clock signals phase-locked to a common reference frequency using phase-locked loop circuits, where frequency errors in one signal are corrected by adjusting the frequency-division ratio, and adjustments are made to the reference clock frequency to independently correct the second signal, allowing for proportional and scheduled corrections to maintain stability across different applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a shared reference clock is used for multiple communication blocks, then cost is minimized, but frequency accuracy and stability are compromised for individual blocks
Solution Approach 1:
The patent segments the frequency control into two independent parts: a shared reference clock and individual frequency control circuits for each communication block. Each block has its own frequency divider and control logic that operates independently on the shared reference, allowing cost reduction through sharing while maintaining individual frequency accuracy through separate control mechanisms.
Solution Approach 2:
The patent introduces frequency control circuits as intermediary components between the shared reference clock and each communication block. These intermediary circuits include frequency dividers and control logic that independently adjust the frequency for each block without affecting others, thus preserving frequency accuracy while enabling shared reference usage.
2Measurement precision
If AFC is used to adjust the reference clock frequency for cellular transceiver tracking, then frequency accuracy is improved, but stability is disrupted for other circuits sharing the reference
Solution Approach 1:
The patent segments the frequency control function so that AFC operates independently on each communication block's frequency control circuit rather than on the shared reference clock itself. This allows the cellular transceiver to track frequency accurately through AFC while other blocks maintain stable frequencies from the unadjusted shared reference.
Solution Approach 2:
The patent applies different frequency control qualities to different blocks: the cellular transceiver receives dynamic AFC adjustments for frequency tracking, while other blocks receive stable, unadjusted frequencies from the shared reference. Each block's frequency control circuit provides locally optimized frequency characteristics suited to its specific requirements.
3Measurement precision
If the reference clock frequency is adjusted for Doppler shift tracking, then frequency accuracy is improved, but performance is impaired in applications requiring clock stability
Solution Approach 1:
The patent segments frequency control so that Doppler compensation through AFC is applied independently to each block's frequency control circuit rather than to the shared reference clock. This allows blocks requiring frequency tracking (like cellular transceivers) to receive Doppler-compensated frequencies while blocks requiring stability (like GPS receivers during measurement intervals) maintain stable frequencies from the unadjusted shared reference.
Solution Approach 2:
The patent provides locally optimized frequency characteristics to different blocks: Doppler-compensated, dynamically adjusted frequencies to blocks needing tracking accuracy, and stable, unadjusted frequencies to blocks requiring measurement stability. Each block's frequency control circuit delivers the appropriate frequency quality for its specific application requirements.
4Measurement precision
If AFC corrections are applied to the reference clock, then frequency accuracy is improved, but disruptions occur in applications requiring clock stability during critical intervals
Solution Approach 1:
The patent segments the frequency control architecture so that AFC corrections are applied independently to each block's frequency control circuit rather than to the shared reference clock. This prevents disruptions during critical intervals because the shared reference remains stable while individual blocks receive their necessary AFC adjustments without affecting others.
Solution Approach 2:
The patent applies frequency control quality locally to each block: blocks requiring frequency tracking receive AFC corrections through their individual frequency control circuits, while blocks requiring stability during critical intervals maintain stable frequencies from the shared reference without AFC disruptions.
Data Source
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AI summary
Methods and circuits for synthesizing two or more signals phase-locked to a common reference frequency signal are disclosed. In one embodiment, a method comprises generating first and second output signals (350, 370) phase-locked to a reference clock signal, using first and second phase- locked loop circuits (200', 200' '). In response to a detected frequency error in the first output signal, the first output signal (350) is corrected by adjusting a frequency-division ratio in the first phase-locked loop circuit. The second output signal (370) is corrected, separately from the correction to the first output signal, by adjusting a frequency-division ratio in the second phase-locked loop circuit, using an adjustment parameter calculated from the detected frequency error. In another exemplary method, first and second output signals are generated as described above, using first and second phase-locked loop circuits. The first output signal is corrected by adjusting a frequency-division ratio in the first phase-locked loop circuit and generating a control signal (360) to adjust the frequency of the reference clock signal, in response to detected frequency error in the first output signal. Because the second output signal (370) is derived from the common reference clock signal, adjustments to the reference clock frequency (FREF) will also adjust the frequency of the second output signal. Additional adjustments to the second output signal (370) may be applied in some embodiments by adjusting a frequency-division ratio in the second phase-locked loop circuits. Circuits for implementing the described methods are also disclosed.