Multi-Package IC Assembly With Central Through-Mold Vias
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Solution Overview
Problem
Integrated circuit assemblies with multiple stacked dies face challenges in reducing size and increasing performance while minimizing yield losses due to manufacturing defects and warpage issues, particularly with through-mold vias (TMVs) around the perimeter of dies, which increase package size and positional tolerance, leading to reduced die-to-die interconnections and increased costs.
Innovation Solution
The use of metallic plated holes electrically coupling substrates between dies within the integrated circuit assembly, allowing for a more compact design by locating these holes between the dies, reducing the distance between substrates, and improving positional tolerance, thus enabling faster signal communication and reducing the number of dies in each package while maintaining the same total number of dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-mold vias (TMVs) are located around the perimeter of dies, then electrical connections between stacked electronic packages are established, but package size increases and positional tolerance worsens
Solution Approach 1:
The patent moves the through-mold vias from the traditional peripheral location (2D arrangement around the die edge) to a central location (3D arrangement between stacked dies). This dimensional repositioning allows the vias to be embedded within the stack height rather than extending the package footprint, thereby reducing package size while maintaining electrical connectivity.
Solution Approach 2:
Instead of placing vias around the perimeter of the die as is conventional, the patent inverts this approach by positioning the vias in the center of the package, between the stacked dies. This inversion transforms the via location from an external peripheral position to an internal central position, improving both package compactness and alignment precision.
2Reliability
If through-mold vias are located around the perimeter of dies, then electrical connections are established, but positional tolerance increases
Solution Approach 1:
The patent inverts the conventional via placement from peripheral to central location. The central positioning between stacked dies provides a more stable reference frame for alignment, reducing positional tolerance issues that arise from peripheral placement where warpage and thermal expansion have greater leverage on alignment accuracy.
Solution Approach 2:
The patent applies local quality by positioning the vias in a specific region (center) with different characteristics than the periphery. The central region between stacked dies experiences less warpage and dimensional variation, providing better positional stability and manufacturing precision for the critical via locations.
3Productivity
If the number of dies or electronic packages increases, then processing and memory capacity increases, but yield losses increase due to warpage
Solution Approach 1:
By repositioning vias to a central 3D location between stacked dies rather than peripheral 2D placement, the patent creates a more compact structure that reduces cumulative warpage effects. This dimensional change allows multiple dies to be stacked with better alignment control, increasing capacity while maintaining yield.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a smaller, more efficient multi-package integrated circuit assembly with improved signal communication and reduced yield losses, as the metallic plated holes can be placed closer to the center of the package, reducing the size of the assembly and increasing the number of connections, making the packages more interchangeable and cost-effective.
Implementation Method 1
a metallic plated hole electrically coupling the first package substrate and the second package substrate
Data Source
AI summary
A multi-package integrated circuit assembly can include a first electronic package having a first package substrate including a first die side and a first interface side. A first die can be electrically coupled to the first die side. A second electronic package can include a second package substrate having a second die side and a second interface side. A second die can be electrically coupled to the second die side. A metallic plated hole can be electrically coupled from the interface side of the first package substrate to the interface side of the second package substrate. A collective substrate can be attached to the first electronic package. For instance, the collective substrate can be located on a face of the first electronic package opposing the first package substrate. The collective substrate is electrically coupled to the first die and the second die through the first package substrate.