Multi-Phase ADPLL Architecture Without TDC for High Phase Resolution
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Solution Overview
Problem
Conventional all-digital phase locked loops (ADPLLs) face an increase in circuit scale to improve time resolution, leading to larger chip area and higher power consumption, due to the need for more delay elements and flip-flops in the time-to-digital converter (TDC).
Innovation Solution
A phase locked loop design that generates multiple feedback clock signals with different phases, using a digitally controlled oscillator and a feedback side frequency divider, which reduces the circuit scale by eliminating the need for a TDC, and includes a reference clock latch circuit, control circuit, and correction circuit to control and correct phase differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of stages of delay elements and flip-flops in the TDC is increased to improve time resolution, then phase measurement precision is improved, but circuit scale increases
Solution Approach 1:
The patent extracts and eliminates the TDC component from the PLL system. Instead of using a TDC that requires multiple stages of delay elements and flip-flops to achieve high time resolution, the invention uses a different architecture where the phase difference is measured by comparing the output clock signal directly with the reference clock signal through frequency dividers and latch circuits, thereby removing the need for complex TDC structures
Solution Approach 2:
The patent replaces the mechanical/TDC-based phase measurement system with a digital signal processing approach. The phase difference information is obtained through frequency division and synchronous latching operations rather than through physical delay elements and flip-flops, substituting a simpler digital system for a more complex hardware-based measurement system
2Measurement precision
If the circuit scale of the ADPLL is increased to improve phase measurement accuracy, then measurement precision is improved, but chip area increases
Solution Approach 1:
The patent removes the TDC component which is the primary consumer of chip area in conventional ADPLLs. By eliminating this component and replacing it with frequency dividers and latch circuits, the chip area is significantly reduced while maintaining or improving phase measurement accuracy through the new measurement mechanism
Solution Approach 2:
The patent uses frequency-divided versions of the clock signals to create multiple measurement paths that can be processed in parallel. By dividing the frequencies of both the reference and output clock signals, the system can measure phase difference at lower frequencies where more precise measurements can be made without requiring additional hardware resources
3Measurement precision
If the number of delay elements and flip-flops is increased to improve time resolution, then phase error reduction is achieved, but power consumption increases
Solution Approach 1:
The patent eliminates the power-hungry TDC component from the system. The TDC typically consumes significant power due to the large number of delay elements and flip-flops that must be continuously operated. By removing this component and using a simpler frequency division and latching approach, power consumption is dramatically reduced while maintaining time resolution capabilities
Solution Approach 2:
The patent employs periodic frequency division operations to measure phase difference. Instead of continuously operating complex TDC circuits, the system periodically divides the clock signals and latches them at specific phases, achieving time resolution measurements through periodic sampling rather than continuous complex circuit operation, thereby reducing average power consumption
Data Source
AI summary
In a phase locked loop composed of digital circuits, the circuit scale of a circuit that generates phase difference information is reduced. A multi-phase clock generation circuit generates a plurality of feedback clock signals having different phases. A feedback side frequency divider divides frequencies of the plurality of feedback clock signals and outputs the feedback clock signals as frequency-divided clock signals. A reference clock latch circuit holds the frequency-divided clock signals in synchronization with a reference clock signal and outputs a held value. A control circuit controls the frequencies of the plurality of feedback clock signals on the basis of the held value.