Multi-Phase Latch Retiming for Timing-Resilient IC Optimization
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Solution Overview
Problem
Traditional integrated circuit design methodologies struggle with performance scaling due to parametric variations from manufacturing processes, power supply voltage, and on-chip temperature, especially in level-sensitive latch-based circuits, as they require logic computation within a clock cycle, limiting improvements in power, performance, and area.
Innovation Solution
Transform edge-triggered flip-flops into equivalent modules comprising multiple-phase level-sensitive latches, applying level-sensitive latch retiming and better-than-worst-case design techniques to optimize signal propagation paths, incorporating timing error prediction and detection mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional synchronous integrated circuit design methodology is used with edge-triggered flip-flops, then timing verification is straightforward with setup and hold time checks, but logic computation must complete within a clock cycle which limits performance improvement and increases power consumption
Solution Approach 1:
The patent changes the fundamental timing parameter constraints by transitioning from edge-triggered flip-flops with fixed setup/hold time requirements to level-sensitive latches where the transparent phase duration becomes the critical parameter. This allows logic computation to extend beyond a single clock cycle boundary, enabling faster effective computation rates while reducing power consumption by allowing asynchronous data arrival within the transparent window.
Solution Approach 2:
The patent introduces dynamic timing behavior through level-sensitive latches where the data capture window is determined by the transparent phase duration rather than fixed edges. This dynamic approach allows the circuit to adapt to varying computation delays without requiring uniform clock cycling, improving overall productivity while reducing unnecessary power consumption from synchronized clock distribution.
2Adaptability or versatility
If level-sensitive latches are used with time borrowing, then data signal can arrive later than latch enable signal, but the borrow time must be compensated in subsequent logic stages which complicates timing analysis
Solution Approach 1:
The patent segments the timing analysis into distinct phases: the transparent phase where time borrowing occurs, and the subsequent phases where compensation must occur. By dividing the timing verification into these segments, the complexity is managed through systematic phase-by-phase analysis rather than attempting to verify the entire clock cycle simultaneously.
Solution Approach 2:
The patent uses the latch transparent phase as an intermediary mechanism that mediates between early and late data arrivals. The transparent phase acts as a buffer window that absorbs timing variations, and the timing analysis methodology uses this intermediary phase to systematically track and compensate for time borrowing across logic stages.
3Area of moving object
If technology scaling is applied to reduce nominal parameter values, then integration density increases, but parametric variations from manufacturing process, power supply voltage, and temperature cause best-case and worst-case values to not scale down proportionally which hinders performance scaling
Solution Approach 1:
The patent applies dynamic timing verification that tracks signal propagation delays through multiple clock phases rather than relying on static worst-case timing constraints. This dynamic approach allows the circuit to tolerate parametric variations better because it verifies actual signal arrival times relative to latch transparent phases rather than enforcing fixed setup/hold margins that do not scale with technology.
Solution Approach 2:
The patent changes the timing verification parameters from fixed setup and hold times to phase-relative arrival time checks. By verifying that signals arrive within the transparent phase window rather than meeting fixed time margins, the design becomes more resilient to parametric variations that do not scale proportionally with technology scaling, maintaining reliability while achieving higher integration density.
Data Source
AI summary
This invention is related to an integrated circuit optimization system and method wherein an edge-triggered sequential element such as a flip-flop is transformed into an equivalent module including level-sensitive latches of multiple phases, subsequently level-sensitive latch-based optimization techniques are applied such as level-sensitive latch retiming and better-than-worst-case design such as based on prediction and detection of signal propagation in a path through a level-sensitive latch, resulting in an integrated circuit including separate level-sensitive latches of multiple phases, edge-triggered sequential elements, and combinational logic networks.