Multi-Plane Memory Block Stripe Testing Without Idle Planes
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Solution Overview
Problem
Conventional multi-plane test operations for memory devices are inefficient due to the inclusion of bad blocks, leading to idle planes and minimal test time reduction, despite the use of smart manufacturing artificial intelligence to predict good blocks, resulting in suboptimal performance and prolonged testing times.
Innovation Solution
Perform multi-plane test operations on dynamically determined block stripes by selecting individual blocks for each plane based on the distribution of bad and good blocks, ensuring no plane remains idle and maximizing efficiency by forming block stripes with sequential good blocks across multiple planes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional multi-plane test operations include bad blocks, then all blocks are tested uniformly, but idle planes occur and test time is prolonged
Solution Approach 1:
The patent changes the parameter of block selection from uniform sequential ordering to dynamic selection based on bad block distribution across planes. By adjusting how blocks are assigned to planes (skipping bad blocks in each plane), the system maintains test completeness while eliminating idle planes and reducing overall test time.
Solution Approach 2:
The patent introduces dynamic block stripe determination that adapts to the actual distribution of bad blocks across planes. Instead of a static sequential testing approach, the system dynamically selects which blocks to test in each plane based on real-time identification of bad blocks, ensuring all active planes remain busy throughout the test process.
2Productivity
If smart manufacturing AI predicts good blocks, then testing efficiency should improve, but minimal test time reduction is achieved due to suboptimal performance
Solution Approach 1:
The patent implements a feedback mechanism where the system first identifies bad blocks in each plane, then uses this information to dynamically determine optimal block stripes for testing. This feedback loop ensures that the AI prediction system adapts to actual bad block distribution, maximizing the utilization of all planes and achieving significant test time reduction rather than minimal improvement.
Solution Approach 2:
The patent performs preliminary identification of bad blocks across all planes before determining the test sequence. By knowing in advance which blocks are bad in each plane, the system can pre-calculate optimal block stripes that maximize parallel testing efficiency, rather than reacting to bad blocks during the testing process itself.
3Ease of manufacture
If blocks are selected sequentially without considering bad block distribution, then the test process is simple, but plane utilization is suboptimal
Solution Approach 1:
The patent segments the testing process into distinct phases: first identifying bad blocks in each plane, then determining optimal block stripes based on this segmentation. This segmentation allows the system to maintain simplicity in the identification phase while achieving optimized utilization in the execution phase, resolving the contradiction between process simplicity and productivity.
Data Source
AI summary
Various embodiments provide for performing a multi-plane test operation on a dynamically determined block stripe of a memory device, which can be part of a memory system, such as a memory sub-system.