Multi-Plane Memory Erase Failure Recovery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As memory cells decrease in size and memory arrays increase in density, maintaining data integrity becomes challenging due to increased manufacturing defects such as shorting between word lines, which can lead to data corruption during programming and erasing operations, especially in multi-plane erase operations.
Innovation Solution
The technology involves performing a multi-plane erase by concurrently erasing multiple planes, and if the erase fails, successively disconnecting individual planes from the others until a multi-plane erase passes, thereby isolating and addressing defective planes without marking all blocks as bad.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-plane erase is performed concurrently, then productivity is improved, but reliability deteriorates due to increased manufacturing defects causing data corruption
Solution Approach 1:
The patent segments the memory system into multiple independent planes that can be erased concurrently. Each plane is treated as a separate erasable unit with its own block structure, allowing parallel erase operations while maintaining the ability to isolate and manage defects in individual planes without affecting others.
Solution Approach 2:
The patent changes the operational parameters by implementing different erase strategies based on defect detection. When manufacturing defects are detected in specific planes, the system adjusts erase parameters to exclude defective blocks from concurrent erase operations, thereby maintaining data integrity while preserving productivity in healthy planes.
2Reliability
If defective blocks are marked as bad to ensure reliability, then data integrity is improved, but productivity deteriorates due to loss of usable memory space
Solution Approach 1:
The patent applies local quality by marking only the specific defective blocks as bad within affected planes, rather than marking entire planes or all blocks across all planes. This localized approach ensures data integrity in defective areas while preserving the usability of good blocks in both the same and other planes, thereby maintaining high memory utilization.
3Reliability
If all blocks are marked as bad when erase fails, then reliability is improved, but productivity deteriorates due to unnecessary loss of good blocks
Solution Approach 1:
The patent extracts and isolates only the defective blocks caused by manufacturing defects when an erase operation fails. By identifying and marking only the specific bad blocks rather than all blocks in the plane, the system recovers and preserves good blocks for future use, reducing unnecessary loss of memory capacity and improving overall productivity.
Data Source
AI summary
An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells disposed in a plurality of planes. The control circuit is configured to concurrently erase a block of memory cells in each of the plurality of planes, determine that the concurrent erase failed, disconnect a first one of the planes from the plurality of planes to form first remaining planes, and concurrently erase a block of memory cells in each of the first remaining planes.