Multi-Plane Memory Programming With Adaptive Voltage Step Size
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Solution Overview
Problem
Multi-plane programming in non-volatile memory devices is inefficient due to the slowest plane determining the programming speed, leading to neighbor plane disturb (NPD) and increased programming time.
Innovation Solution
A method for programming memory devices with multiple planes involves incrementing programming voltage using a first step size, verifying planes, disabling planes with verification exceptions, and adjusting the step size to a second, smaller size for planes that are not disabled, thereby balancing charging and holding times to improve efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-plane programming is used to program two or more planes simultaneously, then programming efficiency is improved, but neighbor plane disturb occurs and programming time increases
Solution Approach 1:
The patent dynamically adjusts the programming voltage step size based on verification results. When verification exceptions occur in certain planes, the step size for those planes is reduced, allowing finer control over the programming process and reducing interference to neighboring planes while maintaining overall programming efficiency
Solution Approach 2:
The patent implements dynamic adaptation of programming parameters during the multi-plane programming process. The control logic circuit monitors verification results in real-time and adjusts programming voltages and step sizes differently for different planes, transforming a static uniform programming approach into a dynamic adaptive one that reduces neighbor plane disturb
2Speed
If programming voltage is incremented with a large step size, then programming speed is improved, but programming precision deteriorates
Solution Approach 1:
The patent dynamically adjusts the programming voltage step size based on verification results. Initially, a larger first step size is used for faster programming, but when verification exceptions are detected, the step size is reduced to a smaller second step size for those specific planes, achieving both speed and precision
Solution Approach 2:
The patent applies different programming step sizes to different planes based on their individual verification results. planes with verification exceptions use a smaller step size for precise programming, while planes without exceptions continue with the larger step size, optimizing both speed and precision locally for each plane
3Device complexity
If all planes are programmed simultaneously with the same programming parameters, then device complexity is reduced, but programming time increases due to the slowest plane
Solution Approach 1:
The patent segments the programming process by plane, allowing each plane to have independent verification and parameter adjustment. This segmentation enables parallel programming of multiple planes while applying different step sizes to different planes based on their specific needs, reducing overall programming time without significantly increasing control complexity
Solution Approach 2:
The patent performs preliminary verification of planes during the programming process. When verification exceptions are detected early, the step size is adjusted for subsequent programming cycles, preventing time waste from re-programming failed planes and optimizing the overall programming schedule
Data Source
AI summary
A method for programming a memory device, a memory device, and a memory system are disclosed. The memory device includes planes. The method includes: programming the planes by using a first programming voltage incremented with a first step size, and programming at least one but not all of the planes by using a second programming voltage incremented with a second step size. The second programming voltage is greater than the first programming voltage, and the second step size is smaller than the first step size.