Multi-port Memory Circuitry Merging Bitcell Arrays
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Solution Overview
Problem
Foundries do not supply 3-port memories, making it difficult to implement advanced processing core designs that require one dedicated write-port and two dedicated read-ports without sacrificing power, performance, and area (PPA).
Innovation Solution
The implementation of multi-port memory circuitry that merges multiple bitcell arrays, reusing existing 2-port memory developed with foundry bitcells, where the write port is shared and read operations are separate, allowing for the creation of efficient 3-port memory devices with reduced area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If multiple separate bitcell memory devices are used to implement 3-port memory, then the required read and write port functionality is achieved, but the area and power consumption increase
Solution Approach 1:
The patent merges multiple 2-port memory bitcell arrays into a single integrated 3-port memory device. The write port logic is shared across both memory arrays, while read port logic is duplicated, allowing simultaneous write and read operations across three ports without requiring separate physical memory devices, thereby reducing overall area and power consumption.
Solution Approach 2:
The write port logic is designed as a universal shared resource that can service both memory arrays. This multi-functional approach allows the same write logic to be reused for writing to either array, eliminating the need for separate write ports and reducing the total logic area and power requirements compared to using separate memory devices.
2Ease of operation
If multiple separate bitcell memory devices are used to implement 3-port memory, then the required read and write port functionality is achieved, but the power consumption increases
Solution Approach 1:
The patent merges multiple 2-port memory bitcell arrays into a single integrated 3-port memory device. The write port logic is shared across both memory arrays, while read port logic is duplicated, allowing simultaneous write and read operations across three ports without requiring separate physical memory devices, thereby reducing overall area and power consumption.
Solution Approach 2:
The write port logic is designed as a universal shared resource that can service both memory arrays. This multi-functional approach allows the same write logic to be reused for writing to either array, eliminating the need for separate write ports and reducing the total logic area and power requirements compared to using separate memory devices.
3Ease of manufacture
If foundry-supplied 1-port or 2-port memories are used, then manufacturing availability is ensured, but the ability to implement advanced processing core designs requiring 3-port memory is limited
Solution Approach 1:
The patent segments a single 3-port memory device into multiple 2-port memory bitcell arrays that can be independently manufactured using standard foundry processes. Each bitcell array can be manufactured separately, but when integrated together with shared write logic and duplicated read logic, they form a functional 3-port memory, thus bridging the gap between foundry capabilities and design requirements.
Solution Approach 2:
The write port logic is designed as a universal shared resource that can service both memory arrays. This multi-functional approach allows the same write logic to be reused for writing to either array, eliminating the need for separate write ports and reducing the total logic area and power requirements compared to using separate memory devices.
Data Source
AI summary
Various implementations described herein are directed to an integrated circuit having multiple bitcell arrays and multiple input ports including a single write input port for the multiple bitcell arrays and multiple read input ports for the multiple bitcell arrays. The integrated circuit may include multiple read output ports for the multiple bitcell arrays. The single write input port is used for writing data to the multiple bitcell arrays, and the multiple read input ports are used separately for reading data from the multiple bitcell arrays for output to the multiple read output ports.