Multi-Port Memory Cell Layout for Read Disturb-Free Access
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Solution Overview
Problem
Existing multi-port memory designs face challenges such as read disturb and write failure, particularly with asynchronous access patterns to multiple ports of the same memory cell, leading to design complexity and increased time to market.
Innovation Solution
The proposed multi-port memory architecture utilizes an inverter circuit cell and a hold circuit cell, along with multiple unit cells configured as either read or write cells using tristate drivers, allowing for efficient configuration and reduced wire usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple read ports and write ports are added to memory cell, then access parallelism is improved, but read disturb and write failure occur due to asynchronous access patterns
Solution Approach 1:
A hold circuit is introduced as an intermediary component between the inverter circuit and multiple unit circuit cells. This hold circuit receives the output signal from the inverter circuit and selectively provides it to either read unit cells or write unit cells based on control signals, thereby mediating the asynchronous access patterns and preventing read disturb and write failure conditions
Solution Approach 2:
The patent implements dynamic configuration of unit circuit cells that can be selectively enabled or disabled based on operational mode. Unit cells have enable signals that dynamically control their participation in read or write operations, allowing the memory system to adapt to different access patterns and avoid harmful asynchronous interactions
2Adaptability or versatility
If traditional multi-port memory architecture is used, then multiple access ports are achieved, but design complexity increases and time to market is extended
Solution Approach 1:
Unit circuit cells are designed with universal functionality to operate as either read unit cells or write unit cells depending on configuration. Each unit cell includes tristate drivers and enable logic that allows the same physical circuit structure to serve multiple functions, eliminating the need for separate dedicated read and write circuit paths and significantly reducing design complexity
Solution Approach 2:
The memory cell is segmented into functional blocks: an inverter circuit, a hold circuit, and multiple configurable unit circuit cells. This segmentation allows independent optimization and configuration of each block, simplifying the overall design process while maintaining multi-port functionality
3Reliability
If read and write assist circuitry is added to prevent read disturb and write failure, then reliability is improved, but device complexity and area increase
Solution Approach 1:
The hold circuit is merged with the inverter circuit output stage, sharing the same physical location and signal paths. This integration eliminates the need for separate assist circuitry while maintaining reliability, as the hold circuit naturally provides the necessary control functionality without requiring additional dedicated read assist or write assist blocks
Solution Approach 2:
The unit circuit cells include self-managing enable logic and tristate drivers that automatically control their own operation based on incoming control signals. This self-service capability eliminates the need for external assist circuitry to manage read and write operations, reducing overall memory footprint while maintaining reliability
Data Source
AI summary
Certain aspects of the present disclosure are directed towards a multi-port memory cell. The multi-port memory cell may include: an inverter circuit cell; a hold circuit cell having an output coupled to an input of the inverter circuit cell and an input coupled to an output of the inverter circuit cell; and multiple unit circuit cells having respective tristate drivers, wherein a first plurality of the multiple unit circuit cells are configured as read circuit cells having inputs coupled to an output of the inverter circuit cell and a second plurality of the multiple unit circuit cells are configured as write circuit cells having outputs coupled to an input of the inverter circuit cell.