Multi-Port SRAM Layout With 3D Metal Routing for Cell Shrink
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Solution Overview
Problem
Multi-port SRAM cells face challenges in reducing cell size due to insufficient area usage in device layer and metal interconnect structures, particularly in the deep sub-micron era, leading to design rule violations and inadequate routing resources.
Innovation Solution
The layout design of multi-port SRAM cells incorporates a two-port SRAM cell with less than seven metal zero tracks, utilizing gate-all-around (GAA) transistors and innovative metal interconnect structures, such as cut-metal-gate (CMG) and continuous-poly-on-diffusion-edge (CPODE) features, to optimize space utilization and routing resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional metal interconnect structures are used in multi-port SRAM cells, then routing resources are sufficient, but cell area becomes excessively large
Solution Approach 1:
The patent introduces cut-metal-gate (CMG) features that extend vertically through the metal interconnect layers, creating three-dimensional routing pathways. This allows signal routes to pass through multiple metal layers via CMG structures, effectively adding a vertical dimension to the interconnect architecture and reducing the horizontal footprint of the SRAM cell.
Solution Approach 2:
The metal interconnect structure is segmented into multiple discrete layers (M0, M1, M2, etc.) with selective connectivity. The CMG features segment the continuous metal paths into controlled segments that can be independently routed through different layers, allowing optimized space utilization while maintaining sufficient routing resources.
2Area of moving object
If cell size is reduced in deep sub-micron era, then integration density increases, but design rule violations occur
Solution Approach 1:
By utilizing vertical CMG structures that penetrate through metal layers, the design achieves three-dimensional routing that reduces horizontal space requirements. This allows cell size reduction while maintaining adequate routing resources and complying with design rules through optimized vertical interconnect placement.
Solution Approach 2:
The CMG features are nested within the metal interconnect layers, with conductive materials embedded within dielectric layers. This nested structure allows multiple functional elements to occupy overlapping spatial regions, reducing the overall cell footprint while maintaining design rule compliance through proper layer stacking.
3Area of moving object
If multi-port SRAM cell area is reduced, then chip integration density improves, but routing resources become insufficient
Solution Approach 1:
The patent employs multi-layer metal interconnects with CMG features that provide vertical routing pathways. This three-dimensional interconnect architecture increases the effective routing capacity without proportionally increasing cell area, as signals can route through multiple layers rather than requiring larger horizontal space.
Solution Approach 2:
The metal interconnect structure is designed with universal CMG features that can serve multiple routing functions. The same CMG structure can carry different signals through different metal layers, providing multi-functional routing capability that maximizes routing resource efficiency within reduced cell area.
Data Source
AI summary
A memory cell includes a device layer including a plurality of transistors and an interconnect structure disposed over the device layer. Each of the transistors includes a gate structure extending lengthwise in a first direction. The interconnect structure includes a bottommost metal line layer electrically coupled to the transistors in the device layer. The bottommost metal line layer includes metal lines arranged in first, second, third, fourth, fifth, and sixth metal tracks in order from first to sixth along the first direction. A distance between any adjacent two of the first, second, third, fourth, fifth, and six metal tracks measured along the first direction is uniform. The first metal track includes a metal line electrically coupled to an electric ground of the memory cell. The sixth metal track includes a metal line electrically coupled to a power supply of the memory cell.