Multi-Power Domain LVS Verification via Automatic Net Annotation
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Solution Overview
Problem
The existing layout-versus-schematic (LVS) methodologies fail to effectively verify the integrity of chip-level power grids in multi-power domain designs, particularly when dealing with multiple power/ground domains, leading to issues such as undetected shorts and opens, and require manual addition of power and ground terminals, which is cumbersome and error-prone.
Innovation Solution
A method and system for implementing multi-power domain digital/mixed-signal verification and low power simulation that automatically generates net/terminal expressions and sets from power data files like CPF or UPF, annotates schematics, and performs LVS checks, enabling automated verification and simulation across multiple power domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If standard LVS methodology treats VDD and GND as global nets, then the verification process is simplified at block level, but it fails to detect shorts and opens between different power domains at chip level
Solution Approach 1:
The patent segments the chip-level power grid into multiple power domains, treating VDD and GND as local nets within each domain rather than global nets. This segmentation enables the LVS tool to verify connectivity integrity within each power domain independently, detecting shorts and opens that would be missed if VDD and GND were treated as globally connected.
Solution Approach 2:
The patent applies local quality by differentiating the treatment of power nets based on their scope: local nets for intra-domain connections and global nets for inter-domain connections. This allows the verification process to adapt to the specific connectivity requirements of each power domain, improving detection accuracy without sacrificing overall process simplicity.
2Measurement precision
If manual addition of power and ground terminals is performed, then verification accuracy may be improved, but the process becomes cumbersome and error-prone
Solution Approach 1:
The patent implements self-service by enabling the LVS tool to automatically identify, annotate, and verify power and ground terminals based on netlist information and configuration files. The tool autonomously determines which nets should be treated as local power/ground nets and performs verification without requiring manual intervention, thereby maintaining accuracy while eliminating procedural complexity and human error.
Solution Approach 2:
The patent applies preliminary action by pre-configuring power domain information and net annotations before the LVS verification process. Configuration files and netlist annotations are prepared in advance to specify which nets are local power/ground nets, allowing the verification tool to automatically apply the correct verification rules without manual terminal addition during the verification step.
3Ease of manufacture
If VDD and GND are treated as global nets at block level, then schematic design process is simplified, but chip-level verification fails under multiple power/ground domains
Solution Approach 1:
The patent applies dynamics by making the treatment of VDD and GND flexible rather than static. The same net can be treated as a global net at the block level for design simplicity, but as a local net at the chip level for verification accuracy. The LVS tool dynamically adjusts its verification approach based on the hierarchical level and configuration information, allowing the design process to maintain simplicity while adapting to multi-power-domain requirements.
Data Source
AI summary
Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more schematics of the electronic circuit design; generating an annotated schematic of the electronic circuit design by automatically annotating at least one of the one or more schematics with some of the one or more net or terminal expression, set, or one or more overriding net or terminal expression; and performing verification of the electronic circuit design by using at least the annotated schematic.