Multi-Rate Receiver Clock Reconfiguration for Arbitrary Data Rates
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Solution Overview
Problem
Conventional transceiver circuitry is limited to specific data rates, making it difficult to support a wide range of data rates required by interfaces like HDMI, which can be costly to adapt with phase-locked loop solutions.
Innovation Solution
The transceiver circuitry is reconfigured to operate at different data rates by using rate detection circuitry to determine the frequency of a reference clock signal and adjusting the clock generation and receiver circuits accordingly, allowing support for arbitrary data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If transceiver circuitry uses predetermined operating rates, then the circuit design is simpler and more cost-effective, but the transceiver cannot support the entire operating range of multi-rate protocols like HDMI
Solution Approach 1:
The transceiver circuitry is designed with dynamic reconfiguration capability, allowing it to adjust its operating parameters (such as clock rates and data rates) based on the detected protocol requirements. This enables the same hardware to adapt to different data rates within the HDMI standard range without requiring multiple fixed-rate transceivers, thereby resolving the contradiction between adaptability and complexity.
Solution Approach 2:
The invention changes the operating parameters of the transceiver circuitry dynamically. By detecting the protocol type and adjusting parameters such as clock multiplication factors, data rates, and timing parameters, the transceiver can support multiple data rates (from 25 MHz to 600 MHz pixel clock rates) using the same physical circuit, thus achieving wide adaptability without proportionally increasing device complexity.
2Adaptability or versatility
If transceiver circuitry is adapted to support arbitrary data rates using phase-locked loop circuitry, then the transceiver can meet requirements of different HDMI applications, but the solution becomes costly
Solution Approach 1:
The transceiver circuitry is designed as a universal platform that can handle multiple HDMI standards and data rates through software-controlled parameter adjustment rather than hardware variations. The same physical transceiver can be configured to support different pixel clock rates (25 MHz to 600 MHz) and corresponding line rates (250 Mbps to 6 Gbps) by loading appropriate configuration parameters, eliminating the need for multiple specialized transceiver designs and reducing manufacturing costs.
Solution Approach 2:
Instead of using expensive phase-locked loop circuitry to generate all possible clock rates, the invention uses a single reference clock and digitally controls the clock generation through parameter tables and configuration data. The system copies the reference clock signal and applies digital multiplication/division factors to generate the required clock rates, which is much more cost-effective than analog PLL approaches while maintaining the ability to support arbitrary data rates within the standard.
3Ease of manufacture
If transceiver circuitry operates at fixed predetermined rates, then the circuit design and manufacturing is simpler, but it limits the transceiver's ability to cover the entire operating range required by HDMI standards
Solution Approach 1:
The invention pre-calculates and stores optimal configuration parameters for various HDMI standards and data rates in lookup tables. When a specific protocol or data rate is detected, the system quickly retrieves the pre-computed parameters (clock multiplication factors, timing values, data rates) and applies them, avoiding complex real-time calculations. This approach maintains manufacturing simplicity while achieving wide protocol compatibility through pre-prepared configuration data.
Data Source
AI summary
Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include rate detection circuitry, receiver circuitry, and configuration circuitry. The receiver circuitry may receive a data stream with an arbitrary data rate. The rate detection circuitry may receive a reference clock signal that is associated with the received data stream. The rate detection circuitry determines the frequency of the reference clock signal such that an appropriate clock signal may be generated for the receiver circuitry. The receiver clock signal may be generated by clock generation circuitry that is coupled to the rate detection circuitry. The configuration circuitry may accordingly configure the receiver circuitry based at least on the determined frequency of the reference clock signal so that the receiver circuitry may operate at the arbitrary data rate.