Multi-Receiver Radar Clock Synchronization with Delay Compensation
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Solution Overview
Problem
Radar systems face challenges in synchronizing data sampling across multiple integrated circuits (ICs) due to high speed, low noise clock fan-out buffers and systemic mismatches, leading to increased cost and complexity, and phase errors in high-resolution angular resolution applications.
Innovation Solution
A radar system with a plurality of receivers, each having its own clock generator, utilizes delay estimation and compensation (DEC) blocks to synchronize clock generators across receivers by generating a sync pulse, measuring delays, and adjusting frequencies to achieve synchronized sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a Clock fan-out buffer is used to synchronize multiple ICs, then clock synchronization is achieved, but cost and device complexity increase due to additional high speed, low noise components on the PCB
Solution Approach 1:
The patent extracts the clock fan-out buffer from the PCB and relocates it inside the first IC. This eliminates the need for additional high-speed, low-noise clock buffers on the PCB, reducing PCB complexity and cost while maintaining synchronization reliability. The buffer is now integrated within the IC itself rather than being a separate PCB component.
Solution Approach 2:
The patent merges the clock buffer function with the first IC by implementing it within the same integrated circuit. This consolidation eliminates separate PCB components and reduces the overall system complexity while achieving the same clock synchronization function.
2Reliability
If a Clock fan-out buffer is used to synchronize multiple ICs, then clock synchronization is achieved, but manufacturing cost increases due to additional high speed, low noise components
Solution Approach 1:
The patent extracts the clock fan-out buffer from external PCB components and relocates it inside the first IC. This eliminates the need to purchase and install additional high-speed, low-noise clock buffers on the PCB, directly reducing manufacturing cost while maintaining synchronization reliability.
Solution Approach 2:
The patent merges the clock buffer function with the first IC, consolidating components to reduce the total bill of materials and assembly steps, thereby reducing manufacturing cost.
3Measurement precision
If multiple ICs are used to process signals from multiple channels, then angular resolution is enhanced, but data sampling alignment across ICs becomes difficult to synchronize
Solution Approach 1:
The patent extracts the clock synchronization function from external PCB components and relocates it inside the first IC. This integration simplifies the synchronization architecture while maintaining the ability to align data sampling across multiple ICs, thus preserving angular resolution without increasing synchronization complexity.
Solution Approach 2:
The patent implements a feedback mechanism where the first IC measures the delay between its internal clock signal and the sync pulse from the second IC, then adjusts the phase of its clock signal to achieve synchronization. This closed-loop approach automatically maintains sampling alignment across ICs without complex external synchronization circuitry.
4Measurement precision
If the sampling rate is increased to maintain phase error within +/â3 deg for a 50 MHz bandwidth system, then measurement precision is improved, but the sampling mismatch requirement becomes extremely tight at 166 ps
Solution Approach 1:
The patent implements a feedback-based phase adjustment mechanism where each IC measures the delay between its clock signal and the sync pulse, then automatically adjusts its clock phase to achieve synchronization. This closed-loop control maintains phase error within +/â3 degrees without requiring extremely tight manufacturing precision of 166 ps, as the system self-corrects for timing variations.
Solution Approach 2:
The patent dynamically adjusts the phase parameter of the clock signal based on measured delay, allowing the system to adapt to timing variations without requiring fixed, extremely tight manufacturing tolerances. This parameter adjustment enables phase error control while relaxing sampling mismatch requirements.
Data Source
AI summary
A radar system comprising a plurality of receivers, each receiver having its clock generator generating a clock signal with a sampling frequency for sampling a radar signal received on one or more receiving antennas and a plurality of delay estimation and compensation (DEC) blocks implemented within the corresponding plurality of receivers, wherein, each DEC block is configured to synchronise the clock generator of one receiver with every other receiver. A method in a radar comprising, generating a sync pulse in a first receiver in the plurality of receives, measuring a delay between the sync pulse and the clock signal in the first receiver, transmitting the sync pulse to other receivers in the plurality of receivers measuring a second delay between the sync pulse and the clock pulse in the other receivers and changing the frequency of the clock generator in the other receivers from the sampling frequency to first frequency for a first time duration.