Multi-Region Chip Substrate for Bulk-SOI Performance Tradeoffs
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Solution Overview
Problem
Integrated circuits fabricated on bulk semiconductor substrates or semiconductor-on-insulator (SOI) substrates face performance limitations due to the inherent characteristics of each substrate type, making it challenging to optimize performance for diverse device types on a single die, as different devices require specific substrate properties, and existing patterning processes can introduce defects that affect semiconductor growth.
Innovation Solution
A multi-function substrate with different regions, including both bulk and SOI regions, is developed, where the base substrate is treated to minimize crystal-originated particle defects, and selective epitaxial growth is used to create regions with varying semiconductor structures, allowing for the formation of diverse devices on a single die with improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bulk semiconductor substrates are used, then device performance is improved, but floating body effects occur
Solution Approach 1:
The substrate is segmented into multiple regions with different structures: a first region with a first semiconductor structure and a second region with a second semiconductor structure. This allows different device types to be formed in different regions, optimizing performance for each device type while mitigating their respective drawbacks.
Solution Approach 2:
Different regions of the substrate are given different local qualities or characteristics. The first region has characteristics suitable for certain device types while the second region has characteristics suitable for other device types, allowing each region to optimize for its specific device type without suffering from the drawbacks of a uniform substrate structure.
2Object-generated harmful factors
If SOI substrates are used, then floating body effects are prevented, but device performance is reduced
Solution Approach 1:
The substrate is divided into multiple regions where the second region uses an SOI structure to prevent floating body effects, while the first region uses a different structure to maintain high device performance. This segmentation allows each region to address its specific requirements.
Solution Approach 2:
The SOI structure with its insulating layer is applied locally to specific regions where prevention of floating body effects is critical, rather than uniformly across the entire substrate. This allows performance optimization in regions where floating body effects are less problematic.
3Ease of manufacture
If a single substrate type is used for all devices, then manufacturing is simplified, but performance optimization for diverse device types is limited
Solution Approach 1:
The substrate is segmented into multiple functional regions that can be formed through selective processing steps. Different semiconductor structures are created in different regions using selective epitaxial growth and patterning, allowing performance optimization for diverse device types while maintaining a unified substrate platform.
Solution Approach 2:
The substrate is designed to serve multiple functions by incorporating different semiconductor structures in different regions. A single substrate can support both high-performance devices requiring one structure type and devices requiring another structure type, making the substrate universally applicable to diverse device types.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-function substrate enables enhanced performance for various device types by optimizing substrate characteristics within different regions, reducing the negative impact of defects and allowing for high-speed, low-power operation alongside preventing floating body effects, thus improving overall chip performance.
Implementation Method 1
selective epitaxial growth is used to create regions with varying semiconductor structures
Data Source
AI summary
The present disclosure relates to an integrated chip. The integrated chip includes a polysilicon layer arranged on an upper surface of a base substrate. A dielectric layer is arranged over the polysilicon layer, and an active semiconductor layer is arranged over the dielectric layer. A semiconductor material is arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.