Multi-Row Die Interconnect Layout for Dense D2D IC Packaging
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Solution Overview
Problem
The challenge in integrated circuits (ICs) is to maximize performance while minimizing size and complexity, as increasing functionality among multiple IC dies requires high bandwidth interconnectivity, which is limited by the number and spacing of die-to-die (D2D) interconnects, restricting the integration level due to the dimensions of interconnect structures and technology constraints.
Innovation Solution
The implementation of multi-row columnar die interconnects in IC packages, where die interconnects are arranged in clusters with specific pitches, allowing for a higher density of D2D interconnects by optimizing the spacing between die interconnect clusters, thereby increasing the number of interconnects along the IC edges and enhancing integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If die interconnects are placed at opposing edges to minimize wire length, then signal propagation time is reduced, but the number of D2D interconnects is limited by interconnect structure dimensions
Solution Approach 1:
The patent transitions from a single-row arrangement of die interconnects to a multi-row columnar arrangement. By organizing interconnects into multiple rows along the IC edges, the solution exploits the dimensional space available on the die perimeter, allowing significantly more interconnects to be packed into the same linear dimension without increasing wire length or propagation delay.
Solution Approach 2:
The die interconnects are segmented into multiple column clusters, where each cluster contains multiple rows of interconnects. This segmentation allows the total number of interconnects to be distributed across multiple organized groups, maximizing the use of available edge space while maintaining manageable pitch dimensions within each cluster.
2Quantity of substance
If die interconnect pitch is reduced to increase D2D interconnect density, then more interconnects fit along IC edges, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different pitch dimensions to different spatial locations. Within each column cluster, a smaller row pitch is used to maximize vertical density. Between column clusters, a larger column pitch is used to provide manufacturing tolerance. This local differentiation of pitch quality allows high density where needed while maintaining manufacturability where tolerances are critical.
Solution Approach 2:
The solution changes the pitch parameters by introducing two distinct pitch values: row pitch (smaller) and column pitch (larger). This parameter differentiation allows the system to achieve high interconnect density through multi-row arrangements while the larger column pitch provides sufficient manufacturing tolerance, effectively decoupling the density requirement from the precision constraint.
3Area of stationary object
If IC size is minimized to reduce device footprint, then packaging efficiency improves, but the number of signals that can be transferred between dies is restricted
Solution Approach 1:
The patent utilizes the two-dimensional space along the IC edges by arranging interconnects in multiple rows rather than a single line. This dimensional exploitation allows the number of signal pathways to increase quadratically with edge length rather than linearly, enabling high signal capacity within a compact package footprint.
Solution Approach 2:
The signal transfer capability is segmented into multiple column clusters, each containing multiple rows of interconnects. This segmentation allows the total signal capacity to be distributed across multiple organized pathways, maximizing the use of available edge space for signal transmission while maintaining a compact overall package size.
Data Source
AI summary
An integrated circuit (IC) package including ICs with multi-row columnar die interconnects has increased die-to-die (D2D) interconnect density in a conductive layer. Positioning the die interconnects in die interconnect column clusters, that each include a plurality of die interconnect rows and two columns, reduces the linear dimension occupied by the die interconnects and leaves room for more D2D interconnects. A die interconnect column cluster pitch is a distance between columns of adjacent die interconnect column clusters and this distance is greater than a die interconnect pitch between columns within the column clusters. Die interconnects may be disposed in the space between the multi-row column clusters and additional die interconnects can be disposed at the D2D interconnect pitch between the die interconnect column clusters. IC packages with ICs including the multi-row columnar die interconnects have a greater number of D2D interconnects for better IC integration.