Multi-row Wiring Member for Semiconductor Devices
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Solution Overview
Problem
Conventional semiconductor device manufacturing processes face challenges in achieving a reliable resin-sealed semiconductor device with reduced steps, minimizing device thickness and size, improving adhesion between plating films and resin, and preventing warpage of the sealing resin, while also eliminating the need for metal sheet removal by etching and forming openings for external terminals.
Innovation Solution
A multi-row wiring member configuration featuring a resin layer with uncovered lower faces for internal terminals, connected wiring portions, and uncovered upper faces for external terminals, along with a metal frame portion around the aggregate of individual wiring members, which allows for adjustable terminal pitches and enhanced adhesion, and a manufacturing method that includes specific resist mask formations and etching steps to achieve these features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional substrate structures with metal sheets and multiple plating layers are used, then terminal portions can be formed with internal and external faces, but the device thickness increases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from a conventional multi-layer stacked structure to a planar integrated structure where terminal portions, wiring portions, and resin sealing are arranged in the same plane. This dimensional reorganization eliminates the need for multiple stacked plating layers, reducing device thickness while maintaining all necessary functional layers including the resin layer for sealing and adhesion.
Solution Approach 2:
The patent merges the functions of multiple separate plating layers (internal terminal plating, external terminal plating, wiring plating) into a single integrated terminal portion structure. By combining these functions in the planar configuration, the patent reduces the overall number of layers and eliminates the need for thick stacked structures, thereby reducing device thickness while maintaining adhesion through the resin layer.
2Ease of operation
If metal sheet removal by etching and opening formation are performed, then external terminals can be accessed, but manufacturing steps increase and productivity decreases
Solution Approach 1:
The patent performs preliminary action by pre-forming the terminal portions with uncovered upper faces during the initial plating process, before the resin sealing step. This allows external terminals to be accessible from the beginning, eliminating the need for subsequent etching and opening formation steps, thereby improving manufacturing efficiency and productivity.
Solution Approach 2:
The patent extracts the unnecessary steps of metal sheet removal by etching and opening formation from the manufacturing process. By designing the terminal portions to have uncovered upper faces from the outset, the patent removes these redundant steps, simplifying the manufacturing process and improving productivity without compromising terminal accessibility.
3Ease of manufacture
If multiple plating layers are stacked with the same shape, then wiring portions are formed, but the pitch of terminals is fixed and adaptability decreases
Solution Approach 1:
The patent applies local quality by allowing different regions of the terminal portion to have different characteristics. The terminal portions can be selectively positioned and sized in different areas of the planar structure, enabling adjustable pitch between internal and external terminals. This local variability allows customization of terminal arrangements while maintaining the overall simplified manufacturing process.
Solution Approach 2:
The patent introduces dynamics by making the terminal pitch and arrangement adjustable rather than fixed. The planar configuration allows flexible positioning of terminal portions according to design requirements, enabling adaptation to different pitch requirements without changing the fundamental manufacturing process, thus providing versatility while maintaining ease of manufacture.
4Reliability
If resin sealing is performed over the entire structure, then device reliability improves, but warpage of the sealing resin occurs
Solution Approach 1:
The patent segments the sealing structure by introducing a resin layer that selectively covers only the wiring portions and internal terminal portions, while leaving external terminal portions uncovered. This segmentation allows the resin to provide sealing where needed without creating excessive stress and warpage across the entire structure, maintaining both reliability and flatness.
Solution Approach 2:
The patent applies local quality by providing resin sealing only in specific regions where it is needed for electrical insulation and mechanical support, rather than covering the entire structure uniformly. This localized sealing approach reduces overall resin stress and prevents warpage while maintaining device reliability in the sealed regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the mass production of highly reliable resin-sealed semiconductor devices with improved adhesion, reduced thickness, and minimized warpage, while eliminating the need for metal sheet removal and opening formation, thereby enhancing productivity and yield.
Implementation Method 1
a plating layer 12 that is to become wiring portions, connected with the first plating layer 11, and a second plating layer 13, which is to become external terminals, formed on partial areas within areas of the plating layer 12 that is to become wiring portions
Implementation Method 2
forming a sealing resin portion 55 by sealing the side where the semiconductor element 53 is mounted
Data Source
AI summary
A multi-row wiring member configured of a plurality of wiring members arrayed in a matrix includes a resin layer, a first plating layer forming internal terminals, a plating layer forming wiring portions and a second plating layer forming external terminals. The first plating layer is formed in the resin layer with lower faces thereof uncovered in a bottom surface of the resin layer. The plating layer forming wiring portions is formed on the first plating layer in the resin layer. The second plating layer is formed in the resin layer on partial areas within areas of the plating layer forming wiring portions, with upper faces thereof being uncovered on a top-surface side of the resin layer. On a bottom-surface side of the resin layer, a metal frame is formed at a margin around an aggregate of individual wiring members arrayed in the matrix.