Multi-stage Switched Capacitor Converter Voltage Regulation
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Solution Overview
Problem
Conventional switched capacitor converters face challenges in achieving precise output voltage regulation over a wide range of power supplies, leading to inefficiencies and large output power variations, especially when the regulated output voltage differs significantly from the ideal voltage.
Innovation Solution
A system comprising a switched capacitor circuit with multiple voltage divider stages and a controller that synchronizes charging during different half-cycles of a clock signal to adjust conversion ratios, reducing the number of required selection switches and enhancing efficiency by providing multiple pseudo-continuous voltage steps for precise voltage regulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a feedback loop is added to adjust the equivalent output resistance to achieve regulated output voltage, then voltage regulation precision is improved, but efficiency decreases when the regulated output voltage is far from the ideal voltage
Solution Approach 1:
The patent implements dynamic conversion ratio adjustment by synchronizing the charging of the second voltage divider circuit stage to different half-cycles of the clock signal. This allows the converter to dynamically select between multiple conversion ratios (M1, M2, M3, M4) based on the relationship between input voltage and desired output voltage, thereby maintaining high efficiency across a wide input voltage range while achieving precise voltage regulation without relying on feedback-loop-based equivalent resistance adjustment.
2Measurement precision
If multiple voltage divider stages are cascaded to achieve high voltage resolution, then voltage precision is improved, but the number of capacitors and switches increases decreasing overall efficiency
Solution Approach 1:
The patent segments the voltage conversion function into two distinct stages: a first voltage divider circuit stage that provides a base conversion ratio, and a second voltage divider circuit stage that can be selectively synchronized to different half-cycles to provide additional conversion ratios. This segmentation allows the system to achieve multiple conversion ratios without requiring a full multi-stage cascaded architecture, thereby reducing the total number of capacitors and switches while maintaining high voltage resolution and efficiency.
3Device complexity
If a fixed topology switched capacitor converter is used, then device complexity is reduced, but line regulation performance is limited resulting in low efficiency and large output power variation
Solution Approach 1:
The patent introduces dynamic control into a relatively simple switched capacitor converter topology by implementing selective synchronization of the second voltage divider circuit stage to different half-cycles of the clock signal. This dynamic approach enables the converter to adapt to wide input voltage variations and maintain good line regulation performance without requiring a complex fixed topology, thereby achieving both simplicity and high line regulation performance across varying operating conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves good line regulation and high efficiency by providing numerous switchable conversion ratios, reducing efficiency drops when the regulated voltage is far from the ideal voltage, and allowing for compact, flexible integration in applications like driver-on-board LED drivers.
Implementation Method 1
A switched capacitor converter (SCC) which transfers energy only utilizing capacitors
Data Source
AI summary
A system comprising: a switched capacitor circuit comprising a plurality of voltage divider circuit stages including a first voltage divider circuit stage coupled to a second voltage divider circuit stage; and a controller configured to supply a clock signal to the first voltage divider circuit stage to provide a first voltage on an output node of the first voltage divider circuit stage during a first half cycle of the clock signal, and a second voltage on said output node during a second half cycle of the clock signal. The second voltage divider circuit stage is configured to charge to an input voltage during a half cycle of the clock signal, and the controller is configured to synchronize charging of the second voltage divider circuit stage to a selected one of (i) the first half cycle of the clock signal, wherein the first voltage is supplied as said input voltage, and (ii) the second half cycle of the clock signal, wherein the second voltage is supplied as said input voltage.