Multi-Terminal Device Stack for 3D Semiconductor Density

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Solution Overview

Problem

Conventional semiconductor device configurations are limited by two-dimensional arrays, which restrict component density and functionality, and attempts at three-dimensional arrangements are complicated due to two-terminal limitations, restricting independent device operations and requiring additional lithography steps.

Innovation Solution

A multi-terminal device stack configuration with independent terminals allows for three-dimensional stacking of devices, enabling independent operation and increased density by using intermediate contact layers and self-aligned fabrication processes to form multiple terminals within a semiconductor die.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If two-dimensional arrays are used for device arrangement, then fabrication is simpler, but component density is limited

Engineering Contradiction:
Improvefabrication simplicityVSAvoidcomponent density
Core Design Contradiction:
Ease of manufactureVSQuantity of substance

Solution Approach 1:

The patent transitions from two-dimensional device arrays to three-dimensional device stacks by adding the vertical dimension. Multiple devices are stacked vertically with intermediate contact layers enabling independent electrical access to each device in the stack, thereby increasing component density without significantly complicating the fabrication process

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If conventional three-dimensional device arrangements are implemented, then component density increases, but device functionality is restricted due to two-terminal limitation

Engineering Contradiction:
Improvecomponent densityVSAvoiddevice functionality
Core Design Contradiction:
Quantity of substanceVSAdaptability or versatility

Solution Approach 1:

The patent segments the electrical connections by introducing intermediate contact layers between stacked devices. Each device in the stack can be independently accessed through dedicated terminals connected to its source and drain regions, enabling multiple devices to operate independently within the three-dimensional stack structure

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediate contact layers as intermediary structures between stacked devices. These contact layers provide independent electrical pathways to each device in the stack, serving as mediators that enable full functionality of each device while maintaining compact three-dimensional integration

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If three or more terminal devices are arranged in conventional three-dimensional configurations, then independent device operations are enabled, but additional lithography steps are required

Engineering Contradiction:
Improveindependent device operationsVSAvoidlithography process complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges the formation of intermediate contact layers with the device fabrication process itself. The intermediate contacts are created using the same lithography and etching steps that define the device structures, eliminating the need for separate additional lithography steps while still enabling independent access to multiple terminals

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12029045B2Multi terminal device stack systems and methods
Publication Date: 2024.07.02 INTEGRATED SILICON SOLUTION CAYMAN INC
  • US12029045B2 patent drawing
  • US12029045B2 patent drawing
  • US12029045B2 patent drawing

AI summary

Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a semiconductor comprises: a first device at a first semiconductor level within a multi terminal device stack; wherein the first device is coupled to a first terminal; a second device at a second semiconductor level within the multi terminal device stack, wherein the second device is coupled to a second terminal; a third terminal is coupled to the second device and a fourth terminal is coupled to the first device, wherein the first terminal and second terminal are independently coupled to the first device and second device respectively. The first terminal, the second terminal, the third terminal and the fourth terminal couple components included in the multi terminal stack to components not included in the multi terminal stack.