Multi-thickness Interconnect Structure for Embedded Electronics

The interconnect structure is segmented into two distinct types: thick interconnect layers with large vias for power semiconductor devices, and thin interconnect layers with small vias for logic semiconductor devices. This segmentation allows each interconnect type to be optimized for its specific electrical requirements while maintaining integration within a single embedded package.

Different regions of the embedded package are assigned different interconnect qualities according to their functional requirements. Power device regions receive thick interconnect layers with large via structures optimized for high current carrying capacity, while logic device regions receive thin interconnect layers with small vias optimized for high routing density. This local quality differentiation resolves the contradiction between structural simplicity and requirement adaptability.

Thick interconnect layers are applied locally only in regions where power semiconductor devices are embedded, rather than uniformly across the entire substrate. This allows the package to achieve high current carrying capacity where needed while maintaining compact dimensions in logic device regions, thus improving overall packaging density.

The patent utilizes vertical layering to accommodate different interconnect thicknesses within a compact planar footprint. Multiple interconnect layers are stacked vertically, with thick power interconnects and thin logic interconnects positioned in different vertical planes, allowing both to coexist without significantly increasing the horizontal package volume.