Multi-thread Processor Error Detection via Instruction Fetch Comparison
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Solution Overview
Problem
Microprocessors in critical applications face challenges in detecting and correcting errors in real-time to prevent catastrophic failures due to transient and permanent faults, which can lead to system malfunctions or total failure.
Innovation Solution
A multi-thread processor architecture with a master and slave processor, utilizing an instruction fetch compare engine and store data compare engine to detect and correct errors by comparing instruction and data fetches across threads, allowing for timely error detection and minimal downtime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-thread processing is implemented to improve productivity, then processing throughput increases, but error detection and correction capability deteriorates without additional verification mechanisms
Solution Approach 1:
The patent implements redundant thread copies that execute identical or related instructions simultaneously. These copy threads serve as verification mechanisms where their results are compared against primary thread results to detect errors. The copying principle allows error detection without significantly impacting the main processing throughput, as the copy threads can operate in parallel with minimal overhead.
Solution Approach 2:
The patent employs feedback mechanisms where thread results are continuously compared and verified. When discrepancies are detected between primary and copy thread results, or between different thread outcomes, the system triggers error correction protocols. This feedback loop ensures that errors are detected and corrected in real-time, maintaining reliability while preserving multi-thread processing productivity.
2Reliability
If error verification mechanisms are added to improve reliability, then error detection capability increases, but device complexity increases
Solution Approach 1:
The patent designs the processor architecture where execution units and registers serve multiple functions. The same execution units that perform primary thread processing also handle copy thread processing and verification operations. Registers are used both for data storage and for holding comparison results. This multi-functionality reduces the need for separate dedicated verification hardware, thereby limiting the increase in device complexity while improving error detection capability.
Solution Approach 2:
The patent merges the error detection and correction functions with the existing multi-thread processing infrastructure. Rather than adding separate independent verification systems, the error detection logic is integrated into the thread execution and result combination pathways. This merging approach allows error verification to occur as a natural byproduct of the multi-thread operation, minimizing additional complexity.
3Measurement precision
If redundant thread execution is used to detect errors, then error detection accuracy improves, but processing time increases
Solution Approach 1:
The patent ensures that redundant thread execution and error detection occur continuously in parallel with primary processing, rather than as sequential checkpoints. The copy threads execute simultaneously with primary threads, and result comparisons are performed continuously as data flows through the pipeline. This continuous parallel operation maintains high processing speed while achieving accurate error detection, as the verification happens without interrupting the main computational flow.
Solution Approach 2:
The patent performs preliminary error detection by executing copy threads and comparing results before final result commitment. By detecting potential errors early in the processing pipeline through preliminary comparison operations, the system can correct errors or trigger rollback mechanisms before erroneous results propagate further, thereby minimizing the overall processing time penalty while maintaining high detection accuracy.
Data Source
AI summary
A master processor is configured to execute a first thread and a second thread designated to run a program in sequence. A slave processor is configured to execute a third thread to run the program in sequence. An instruction fetch compare engine is provided. The first thread initiates a first thread instruction fetch for the program and stored in an instruction fetch storage. Retrieved data associated with the fetched first thread instruction is stored in a retrieved data storage. The second thread initiates a second thread instruction fetch for the program. The instruction fetch compare logic compares the second thread instruction fetch for the program with the first thread instruction fetch stored in the instruction fetch storage for a match. When there is a match, the retrieved data associated with the fetched first thread instruction is presented from the retrieved data storage, in response to the second thread instruction fetch.