Multi-tier Memory Stack Non-overlapping Support Pillars
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently integrating non-overlapping support pillar structures, which are crucial for maintaining structural integrity and preventing electrical leakage, while existing methods often result in physical contact or overlap between support pillars, leading to collateral damage and reduced performance.
Innovation Solution
The implementation of a multi-tier three-dimensional memory device structure with first and second support pillar structures that do not overlap or come into physical contact, where the second support pillar structures are laterally spaced from the first support pillar structures, providing structural support without electrical shorts and minimizing collateral etch damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If support pillar structures are formed in three-dimensional memory devices, then structural integrity is improved, but physical contact or overlap between support pillars causes electrical leakage and collateral damage
Solution Approach 1:
The patent introduces a vertical tiered architecture where support pillars are distributed across multiple height levels (first tier and second tier). By transitioning from a single-plane to a multi-level spatial arrangement, the design enables structural support without lateral overlap or physical contact between support pillars, thereby preventing electrical leakage while maintaining mechanical integrity.
Solution Approach 2:
The support structure is segmented into multiple independent support pillars distributed across different tiers. Instead of using a continuous or overlapping support system, the patent divides the support function among discrete, spatially separated pillars that operate independently, eliminating harmful electrical interactions while collectively providing structural stability.
2Reliability
If non-overlapping support pillar structures are implemented, then electrical leakage is prevented, but manufacturing complexity increases due to multi-tier formation processes
Solution Approach 1:
The patent combines multiple formation processes into integrated manufacturing sequences. The first and second tier structures are formed using coordinated deposition and etching operations that simultaneously establish multiple tiers of support pillars. By merging these processes, the patent reduces the total number of discrete manufacturing steps despite the increased structural complexity.
Solution Approach 2:
The patent employs preliminary patterning and deposition steps that pre-establish the spatial framework for multi-tier support pillars. sacrificial layers and template structures are formed in advance to guide subsequent self-aligned etching and deposition processes, ensuring precise non-overlapping positioning without requiring complex real-time control during manufacturing.
3Strength
If support pillars are laterally spaced apart, then structural support is maintained, but device area increases reducing memory density
Solution Approach 1:
The patent resolves the area constraint by utilizing the vertical dimension. Support pillars are arranged in multiple tiers at different heights, allowing lateral spacing to be minimized in the horizontal plane while maintaining structural support through vertical distribution. This three-dimensional arrangement increases memory device density by freeing up horizontal space that would otherwise be required for single-tier support structures.
Solution Approach 2:
The multi-tier support structure implements a nested arrangement where second tier support pillars are positioned to utilize the vertical space above and between first tier pillars. This nesting strategy allows compact packing of support elements in the lateral direction while maintaining adequate spacing for structural support, effectively reducing the overall device footprint.
Data Source
AI summary
A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support openings and first memory openings, filled with first support pillar structures and sacrificial pillar structures, respectively, are formed through the first tier structure. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed thereabove. Second support openings and second memory openings are formed through the second tier structure such that the second support openings do not overlap with the first support pillar structures and the second memory openings overlie the sacrificial pillar structures. Inter-tier memory openings are formed by removal of the sacrificial pillar structures. Memory stack structures and second support pillar structures are formed in the inter-tier memory openings and the second support openings, respectively.