Multi-Tile Processing Array Synchronization via Common Clock
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Solution Overview
Problem
In parallel computing using multiple processor tiles, existing technologies face challenges in synchronizing workloads effectively across tiles, particularly in bulk synchronous parallel (BSP) computing protocols, where dependencies between tiles can lead to inefficiencies and lack of time determinism in data exchange.
Innovation Solution
A computer architecture with a plurality of processing units connected by a switching fabric, utilizing a synchronization module to control the transition between compute and exchange phases, where processing units execute instructions according to a common clock, enabling time deterministic data packet transmission and reception without destination identifiers, ensuring synchronized data exchange across tiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If barrier synchronization is used to ensure all tiles complete compute phases before exchange phases, then data dependency correctness is maintained, but system throughput and productivity deteriorate due to idle waiting time
Solution Approach 1:
The patent applies preliminary action by having tiles indicate completion of their compute phases before the actual phase transition occurs. The synchronization module collects these completion indications and only initiates the exchange phase after all tiles have signaled readiness, eliminating idle waiting time while maintaining data dependency correctness.
Solution Approach 2:
The patent implements feedback through a synchronization module that monitors completion status of each tile's compute phase and uses this feedback information to control the timing of phase transitions. This feedback mechanism ensures that exchange phases begin only when all tiles are ready, optimizing throughput without sacrificing reliability.
2Measurement precision
If destination identifiers are included in data packets for precise routing, then data exchange accuracy is improved, but communication overhead and device complexity increase
Solution Approach 1:
The patent extracts the destination identification function from the data packet itself and implements it through a separate switching fabric mechanism. Data packets are transmitted without destination identifiers, reducing communication overhead, while the switching fabric independently handles routing based on the time-deterministic exchange schedule.
Solution Approach 2:
The patent introduces a switching fabric as an intermediary between data packets and their destinations. This mediator handles the routing function separately from the data transmission, allowing packets to be simplified while maintaining accurate delivery through the fabric's switching logic controlled by the synchronization module.
3Reliability
If time deterministic guarantees are implemented through synchronized clocking, then predictability and reliability are improved, but flexibility and adaptability in handling variable workloads deteriorate
Solution Approach 1:
The patent applies dynamics by allowing the synchronization module to adapt the timing and duration of compute and exchange phases based on actual workload conditions. While maintaining time-deterministic guarantees within each phase, the system can dynamically adjust phase lengths and frequencies to accommodate variable workloads, balancing predictability with flexibility.
Data Source
AI summary
The invention relates to a computer comprising: a plurality of processing units each having instruction storage holding a local program, an execution unit executing the local program, data storage for holding data; an input interface with a set of input wires, and an output interface with a set of output wires; a switching fabric connected to each of the processing units by the respective set of output wires and connectable to each of the processing units by the respective input wires via switching circuitry controllable by each processing unit; a synchronisation module operable to generate a synchronisation signal to control the computer to switch between a compute phase and an exchange phase, wherein the processing units are configured to execute their local programs according to a common clock, the local programs being such that in the exchange phase at least one processing unit executes a send instruction from its local program to transmit at a transmit time a data packet onto its output set of connection wires, the data packet being destined for at least one recipient processing unit but having no destination identifier, and at a predetermined switch time the recipient processing unit executes a switch control instruction from its local program to control its switching circuitry to connect its input set of wires to the switching fabric to receive the data packet at a receive time, the transmit time and, switch time and receive time being governed by the common clock with respect to the synchronisation signal.