Multi-Via Redistribution Layer for Integrated Circuit Packaging

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Solution Overview

Problem

Conventional integrated circuit packaging designs with solder balls are prone to cracking due to stress and warpage from thermal expansion and contraction, particularly at the interface between the redistribution layer and the solder ball, leading to high resistance and potential failure.

Innovation Solution

The design incorporates a redistribution layer with a large number of via structures directly beneath the solder ball footprint, eliminating the need for under-ball metallization and dielectric layers, which reduces stress and warpage by providing a more symmetrical and robust electrical connection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional single-via redistribution layer design is used, then device complexity is reduced, but reliability deteriorates due to cracking from stress and warpage

Engineering Contradiction:

Improvecrack resistanceVSAvoidvia structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The single via structure is segmented into multiple via structures arranged in an array beneath the solder ball footprint. This segmentation distributes the mechanical stress and thermal expansion forces across multiple connection points, preventing crack propagation that would occur in a single via design. The segmented via array maintains electrical connectivity while improving structural reliability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The design changes the geometric parameters of the via structures, specifically making the via diameter substantially equal to the opening diameter in the passivation layer. This parameter optimization allows the via material to extend substantially to the surface, creating a more robust connection that better withstands thermal stress and warpage forces compared to conventional smaller via designs.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If via structures are extended to surface, then electrical conductivity is improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improveelectrical connection qualityVSAvoidvia formation precision

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The via structures are designed with specific dimensional parameters where the via diameter is substantially equal to the opening diameter in the passivation layer. This parameter matching simplifies the manufacturing process by aligning the via formation with the existing opening pattern, reducing the need for additional precision steps while ensuring the via material extends substantially to the surface for optimal electrical conductivity.

Inventive Principle:

Principle #35Parameter changes

3Device complexity

If under-ball metallization and dielectric layers are eliminated, then device complexity is reduced, but stress distribution worsens

Engineering Contradiction:

Improvelayer structure complexityVSAvoidstress distribution

Core Design Contradiction:

Device complexityVSStress or pressure

Solution Approach 1:

The design extracts and eliminates the under-ball metallization and additional dielectric layers from the conventional structure. By removing these intermediate layers, the via structures are directly exposed at the surface beneath the solder ball, simplifying the overall layer structure. The via material itself serves as the stress-distributing element, with its array configuration providing adequate stress management without requiring additional layers.

Inventive Principle:

Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration significantly reduces the likelihood of cracking in the redistribution layer while maintaining low resistance between the solder ball and the top metal layer, enhancing the reliability and durability of the integrated circuit packaging.

Implementation Method 1

Material of the RDL fills the openings in the passivation layer to form via structures that electrically connect the RDL to the top metal conducting layer

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

cracking can occur within the RDL layer near the interface between the solder ball and the nearest via due to stress and warpage of the RDL layer resulting from repeated thermal expansion and contraction

Methodology Applied

Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS10192837B1Multi-via redistribution layer for integrated circuits having solder balls

Publication Date: 2019.01.29 CHIP PACKAGING TECH LLC

AI summary

A wafer-level chip-scale package (WLCSP) includes an integrated circuit (IC) chip, and die bonding pads with a redistribution layer (RDL) having multiple via structures located directly below the footprint of a solder ball placed on the bonding pad. The via structures electrically connect the solder ball to a top metal layer of the IC chip. The RDL may extend beyond the solder ball's footprint and have additional vias that connect to the top metal layer, including vias located under and connected to other solder balls. The bonding pads have a low R-on resistance and are not susceptible to thermal-induced cracking.