Multi-wordline Test Control Circuit for Semiconductor Memory

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Solution Overview

Problem

Conventional wordline test control circuits in semiconductor integrated circuits experience high power consumption and noise, potentially damaging memory banks, due to the simultaneous enabling and prolonged activation of wordlines during testing.

Innovation Solution

A multi-wordline test control circuit that generates specific test signals to activate only the necessary wordlines in a selected memory bank and cell matrix, reducing power consumption and controlling the test modes between active and precharging modes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all wordlines are simultaneously enabled during 1/4 wordline test, then testing coverage is improved, but power consumption increases

Engineering Contradiction:

Improvetesting coverageVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The test control circuit segments the wordline activation into multiple phases. Instead of enabling all wordlines simultaneously, the circuit divides them into groups (e.g., 1/4 wordline groups) and activates them sequentially through different test modes (T14WL, TEWL, TOWL signals), thereby reducing the number of simultaneously active wordlines and lowering power consumption while maintaining comprehensive testing coverage.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The test control circuit implements periodic activation of wordlines through cyclic testing phases. Each test mode (1/4 wordline, even wordline, odd wordline) represents a periodic phase where specific wordline groups are activated in turn, allowing the system to achieve full coverage over time without sustained high power consumption from continuous simultaneous activation.

Inventive Principle:

Principle #19Periodic action

2Productivity

If previously enabled wordlines are maintained in enabled state during sequential testing, then testing continuity is improved, but noise increases and memory banks may be damaged

Engineering Contradiction:

Improvetesting continuityVSAvoidnoise and potential damage

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The test control circuit prepares for the next test phase by pre-managing the state of wordlines. Before transitioning to a new test mode, the circuit ensures that previously activated wordlines are properly disabled and the system is reset to a safe state, preventing noise accumulation and potential damage while maintaining testing continuity through controlled transitions between test modes.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The test control circuit monitors the state of active wordlines and provides feedback control to manage their activation and deactivation. Based on the current test mode and detected conditions, the circuit dynamically adjusts which wordlines remain active and which are disabled, ensuring that noise levels are controlled and memory banks are protected while maintaining necessary testing continuity.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS7626875B2Multi-wordline test control circuit and controlling method thereof

Publication Date: 2009.12.01 SK HYNIX INC

AI summary

A multi-wordline test control circuit in a semiconductor integrated device for performing a multi-wordline test in a specified cell mat among a plurality of cell mats. The multi-wordline test control circuit comprises a multi-test control block for receiving a multi-wordline test signal and outputting a first test signal and a second test signal, and a multi-wordline test block for performing the multi-wordline test in a specified cell mat among a plurality of cell mats in response to the first test signal and the second test signal.