Multi-Write ROM Array Using Source-Read Low-Voltage Cells
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Solution Overview
Problem
Existing non-volatile memory technologies face challenges with slow writing and erasing speeds due to high-voltage operations that can alter threshold voltages and reduce the number of writing activities, primarily through Fowler-Nordheim tunneling.
Innovation Solution
A high-speed multi-write read only memory array design that reads current from the source instead of the drain, using lower voltages to minimize electron impact on gate threshold voltages, allowing for faster and multiple writes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-voltage operation is used for writing and erasing non-volatile memory, then the writing and erasing functions can be achieved, but the threshold voltage changes and the number of writing activities is reduced
Solution Approach 1:
The patent inverts the conventional reading approach by reading from the source terminal instead of the drain terminal. This inversion allows the memory cell to be read without applying high voltage to the drain, thereby preventing threshold voltage changes and enabling multiple write operations while maintaining reliability
Solution Approach 2:
The patent changes the voltage application parameters by using lower voltages during read operations and selectively applying high voltage only during write/erase operations. This parameter change ensures that threshold voltage remains stable during reads, allowing multiple writes without degradation
2Reliability
If Fowler-Nordheim tunneling is used for writing and erasing, then non-volatile memory can be programmed, but the writing and erasing time is greater than 1 millisecond
Solution Approach 1:
The patent employs periodic pulsed voltage applications instead of continuous high-voltage operation. By using short, intense voltage pulses, the tunneling effect is activated only when needed, significantly reducing the overall write/erase time while maintaining data retention capabilities
Solution Approach 2:
The patent modifies the voltage time-profile by using high-voltage pulses of reduced duration. This parameter change allows the memory to achieve the necessary tunneling effect for programming/erasing in less than 1 millisecond while still ensuring reliable data retention
3Productivity
If high voltage is applied to the drain for writing and erasing, then electrons can enter the gate to change threshold voltage, but this reduces the number of writing activities
Solution Approach 1:
The patent inverts the conventional operation mode by performing reads from the source terminal. This inversion eliminates the need for high-voltage drain operations during reads, preventing threshold voltage changes that would limit the number of write activities, thereby improving both writing speed and reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves high-speed writing and multi-write capabilities by reducing voltage requirements, thereby minimizing threshold voltage changes and enhancing operational efficiency.
Implementation Method 1
Compared with the Fowler-Nordheim tunneling, the read-only memory array can use a lower voltage to achieve high-speed writing and multi-write purposes
Data Source
AI summary
A high-speed multi-write read only memory array includes word lines, select lines, bit lines, and sub-memory arrays. There are a first word line, a first select line, a second select line, a first bit line, a second bit line, a third bit line, and a fourth bit line. Each sub-memory array includes a first memory cell coupled to the first word line, the first select line, and the first bit line, a second memory cell coupled to the first word line, the first select line, and the second bit line, a third memory cell coupled to the first word line, the second select line, and the third bit line, and a fourth memory cell coupled to the first word line, the second select line, and the fourth bit line.