Multi-Band Clock Generator with Adaptive PLL Frequency Locking
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Solution Overview
Problem
Wide-band frequency synthesizers using phase-locked loop (PLL) circuits face prolonged locking times due to the increased number of voltage controlled oscillator (VCO) operating characteristic curves, which hinder fast frequency lock mode operations in applications requiring rapid frequency adjustments.
Innovation Solution
A multi-band clock generator incorporating a phase-locked loop (PLL) integrated circuit and an adaptive frequency calibration (AFC) circuit that employs a lookup table and a jumping algorithm to quickly select a multi-bit control word, reducing the number of frequency comparisons needed to lock the VCO output signal to a target frequency sub-band.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the frequency range covered by the synthesizer is increased, then the frequency coverage is improved, but the locking time is prolonged
Solution Approach 1:
The frequency range is divided into multiple sub-bands, each with its own characteristic curve. The AFC circuit segments the control word search space by determining which sub-band the target frequency belongs to, then only searching within that sub-band's control words. This segmentation reduces the total number of control words that need to be searched while maintaining wide frequency coverage.
Solution Approach 2:
The system pre-establishes multiple characteristic curves corresponding to different frequency sub-bands and stores the relationship between control words and frequencies in a lookup table. Before frequency locking, the AFC circuit preliminarily determines the appropriate sub-band and retrieves the corresponding control word range, avoiding a complete search of all possible control words during the locking process.
2Measurement precision
If the number of VCO operating characteristic curves is increased, then the frequency resolution is improved, but the number of frequency comparisons required is increased
Solution Approach 1:
The control word space is segmented into multiple sub-bands, each associated with a specific characteristic curve. The AFC circuit with lookup table segments the search process by first identifying the target sub-band and then only searching control words within that segment. This reduces the total number of frequency comparisons needed while maintaining fine frequency resolution through the use of multiple characteristic curves.
Solution Approach 2:
The system preliminarily determines the appropriate sub-band and retrieves the corresponding control word range from the lookup table before performing frequency comparisons. This preliminary action filters out control words from other sub-bands that would not match the target frequency, reducing the number of actual frequency comparisons required while maintaining high frequency resolution.
Data Source
AI summary
A multi-band clock generator includes a phase-locked loop (PLL) integrated circuit responding to first and second clock signals, and includes a multi-band voltage controlled oscillator (VCO) responding to a multi-bit control word that sets a frequency characteristic curve of the VCO. The multi-band clock generator also includes an adaptive frequency calibration (AFC) circuit responding to the first and second clock signals, and the AFC circuit is configured to look-up a first multi-bit control word during an operation to lock an output clock signal generated by the VCO to a first frequency characteristic curve associated with the first multi-bit control word.