Multi-Bit Flip-Flop Scan Delay for Hold Time Violations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Synchronous circuits in semiconductor devices face timing violations due to clock skew, which existing static timing analysis methods struggle to address effectively, particularly in hold time violations within scan paths.
Innovation Solution
The integration of scan input circuitry that delays the scan input signal by using buffers and NOR gates within the master-slave flip-flop, allowing for improved hold time by selectively passing either the data signal or the delayed scan input signal based on a scan enable signal, thereby enhancing the operational timing of the flip-flop during both functional and scan testing modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan input signal delay is increased to mitigate hold time violations, then hold time is improved, but device complexity increases due to additional external circuitry
Solution Approach 1:
The patent combines the scan input signal delay function with the existing buffer circuitry inside the flip-flop by coupling the delayed scan input signal to the master latch input. This integration eliminates the need for separate external delay circuitry, thereby reducing device complexity while maintaining improved hold time performance.
Solution Approach 2:
The patent uses the existing buffer circuitry within the flip-flop as an intermediary element to delay the scan input signal. By utilizing the buffer's inherent delay characteristics and coupling it to the master latch, the patent achieves signal delay without adding complex external circuitry, thus resolving the contradiction between reliability improvement and device complexity.
2Measurement precision
If buffer delay is derated during static timing analysis, then timing accuracy is improved, but productivity decreases due to additional analysis complexity
Solution Approach 1:
The patent enables the buffer circuitry to serve dual purposes: its primary function and its delay function for scan input signaling. By utilizing the buffer's inherent delay characteristics without requiring separate delay circuitry, the patent simplifies static timing analysis while maintaining accurate timing measurements, thus improving productivity without sacrificing timing precision.
3Ease of manufacture
If routing requirements are simplified by reducing external circuitry, then ease of manufacture is improved, but hold time mitigation capability may be reduced
Solution Approach 1:
The patent merges the delay function with the internal buffer circuitry, eliminating the need for separate external delay circuitry and simplifying routing requirements. This integration maintains hold time mitigation capability by utilizing the buffer's inherent delay characteristics, thus achieving ease of manufacture without compromising reliability.
Solution Approach 2:
The patent uses the internal buffer as an intermediary to provide both signal buffering and delay functions. This approach simplifies routing by eliminating external delay circuitry while maintaining adequate hold time mitigation through the buffer's inherent delay, thereby resolving the contradiction between ease of manufacture and reliability.
Data Source
AI summary
Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.