Multi-Bit Flip-Flop Sharing Using Unidirectional FETs
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Solution Overview
Problem
Flip-flops in computing devices consume significant power, particularly due to dynamic clocking, which limits performance and battery life, and existing solutions like lowering supply voltage or using ultra-low-temperature operation come with performance and cooling challenges.
Innovation Solution
The use of unidirectional/asymmetrical FETs in multi-bit flip-flop circuits for device sharing, reducing clock transistor gate capacitance and enabling tri-state keeper and pass gate sharing to minimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional bidirectional FETs are used in flip-flop circuits, then the circuit can operate with standard clock signals, but the clock transistor gate capacitance is high leading to significant power consumption
Solution Approach 1:
The patent applies asymmetry by using unidirectional FETs instead of conventional bidirectional FETs. The unidirectional FETs have asymmetric current flow characteristics that allow them to function as clock transistors with reduced gate capacitance. This asymmetric device structure enables the clock signal to charge the gate capacitance in one direction while preventing discharge in the opposite direction, thereby reducing the effective capacitance that needs to be charged each clock cycle and lowering dynamic power consumption.
Solution Approach 2:
The patent merges multiple clock transistors into shared keeper devices that are commonly used across multiple flip-flops. By combining the clock transistor functionality with keeper circuitry and making these devices shared resources, the total number of clock transistors is reduced. This merging approach decreases the overall clock transistor gate capacitance that must be charged and discharged during clock operations, directly reducing power consumption.
2Use of energy by moving object
If device sharing is implemented to reduce power consumption, then clock power is reduced by over 40%, but the circuit design complexity increases
Solution Approach 1:
The patent implements universality by designing keeper devices that serve multiple functions: they act as clock transistors, data transmission gates, and data hold elements simultaneously. These multi-functional devices are shared across multiple flip-flops, allowing a single device structure to perform what would traditionally require separate dedicated components for each flip-flop. This multi-functionality reduces the total device count and power consumption while the modular design approach keeps the increased design complexity manageable.
3Device complexity
If unidirectional FETs are used instead of bidirectional FETs, then clock transistor gate capacitance is reduced, but the availability of unidirectional devices may be limited
Solution Approach 1:
The patent applies parameter changes by modifying the electrical characteristics of conventional FETs to create unidirectional behavior. This can be achieved through asymmetric doping profiles, unequal source-drain dimensions, or biased operating conditions that prevent current flow in one direction while allowing it in the other. By changing the operational parameters rather than requiring entirely different device structures, the patent makes unidirectional FETs compatible with existing manufacturing processes while achieving the desired reduced gate capacitance effect.
Data Source
AI summary
Embodiments herein relate to a multi-bit flip-flop circuit which uses unidirectional transistors to allow sharing of transistors among a set of flip-flops, while avoiding charge sharing within or between the flip-flops. Clock devices in the circuit can be shared to reduce the clock transistor gate capacitance and associated power consumption. The shared transistors can provide keeper circuits and/or tri-state inverters in a primary latch and a secondary latch in each flip-flop. One example implementation uses tri-state keeper sharing. Another example implementation uses tri-state keeper and/or pass gate sharing. Another example implementation uses pass gate sharing and no keeper.