Multibit Memory Cell Sensing Circuit for Complementary Bit Disturb
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Solution Overview
Problem
Conventional multibit memory devices face reliability issues due to cross-interaction between spatially separated physical bits in charge-trapping layers, leading to Complementary Bit Disturb (CBD) as devices age, which affects data retention and requires costly solutions like reducing device density or operating in 1-Bit-Per-Cell configuration.
Innovation Solution
The implementation of control circuitry that allows for individual reading of bit values from multiple physical bit locations within a shared charge-trapping layer of a multibit memory cell, using averaging or differential sensing approaches to determine the logic state of the cell, thereby improving reliability without the need for significant area or cost penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multibit memory cells operate at higher densities with smaller transistor architectures, then circuit density and storage capacity improve, but cross-interaction between spatially separated physical bits increases causing Complementary Bit Disturb and reliability loss
Solution Approach 1:
The patent segments the sensing process into multiple independent sensing operations, where each physical bit location is sensed separately through individual bit lines. This allows the memory cell to maintain high density with multiple bit locations while preventing cross-interaction by isolating the sensing of each bit, thereby resolving the contradiction between circuit density and data retention reliability
Solution Approach 2:
The patent introduces control circuitry as an intermediary that manages the sensing process. This control circuitry selectively activates specific bit lines and sense amplifiers to read individual physical bit locations, preventing direct cross-interaction between spatially separated bits while enabling high-density operation. The intermediary control logic ensures that only one bit location is sensed at a time, maintaining reliability despite high density
2Quantity of substance
If multibit memory cells use spatially separated physical bits in the same charge-trapping layer to store multiple bits per cell, then storage capacity improves, but cross-interaction between bits leads to Complementary Bit Disturb affecting stored information
Solution Approach 1:
The patent segments the read operation into separate sensing paths for each physical bit location. Each bit location has its own bit line and sense amplifier connection, allowing multiple bits to be stored in the same charge-trapping layer while preventing cross-interaction during sensing. This segmentation maintains both high storage capacity and information integrity
Solution Approach 2:
The patent applies local quality by providing dedicated sensing resources (bit lines and sense amplifiers) to each physical bit location. This localized sensing approach allows each bit to be read independently without affecting other bits in the same cell, thereby maintaining information integrity while enabling multi-bit storage in high-density configurations
3Device complexity
If conventional sensing approaches are used for multibit memory cells, then device complexity remains low, but Bit Error Rates increase near end-of-life due to Complementary Bit Disturb
Solution Approach 1:
The patent implements dynamic sensing control where the control circuitry adaptively selects which bit lines and sense amplifiers to activate based on the specific read operation required. This dynamic approach allows the system to handle multiple bit locations with enhanced reliability while keeping the average complexity low by only activating necessary sensing paths rather than maintaining all sensing resources simultaneously active
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances data retention and reliability by reducing Bit Error Rates near the end-of-life of multibit memory cells, maintaining high performance at higher circuit densities without the need for reference currents in differential sensing.
Implementation Method 1
a charge-trapping gate stack 102 including a control gate 104, a top or blocking dielectric layer 106, a charge-trapping layer 108
Implementation Method 2
Through proper biasing the MirrorBit cell 100 can store two spatially separated physical bits (bit1 and bit2) as charges at opposite ends of the charge-trapping nitride layer 108
Data Source
AI summary
Memory devices and methods for operating the same are provided. Generally, the device includes an array of multibit-memory-cells, each operable to store multiple bits in separate locations of a charge-trapping layer, and control-circuitry coupled to the array. The control-circuitry is operable read 1st and 2nd bit values of each cell individually based on generated first and second sensed currents, where the first and second sensed currents correspond to charges trapped in first and second bit locations. The control-circuitry executes an algorithm based on the first and second sensed currents and determines a logic state of the cell. In one embodiment, the control-circuitry averages the sensed currents, and compares this to a reference current to determine the logic state. In another, the 2nd bit value is a complement of the 1st, and the control-circuitry compares the currents to determine the logic state without use of a reference current.