Multi-Bit Non-Volatile Memory Cell Layout With Sequential Word-Line Readout
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Solution Overview
Problem
Existing semiconductor devices face challenges in storing multi-bit data efficiently within a smaller area, particularly in non-volatile memory cells like ROM, which limits integration and increases size.
Innovation Solution
A semiconductor device with non-volatile memory cells that utilize a single transistor per memory cell, coupled to word or sub-word lines and a ground voltage node, and a control circuit to activate these lines with a one-cycle clock signal, enabling multi-bit data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If non-volatile memory cells store multi-bit data using single transistor per cell, then memory cell array size is reduced and integration is improved, but data reading complexity increases due to sequential word line activation
Solution Approach 1:
The patent segments the word lines into multiple sub-word lines (first sub-word line, second sub-word line, third sub-word line) that can be activated sequentially. This segmentation allows the memory cell array to store multi-bit data in each cell while maintaining a compact structure. The sequential activation of sub-word lines enables complex data reading operations to be broken down into manageable steps, resolving the contradiction between reduced array size and increased reading complexity.
2Adaptability or versatility
If multiple memory cells are connected to the same bit line, then device integration is improved, but signal interference between cells increases
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit line to a reference potential before reading operations. This preliminary step ensures that the bit line is in a known state, allowing subsequent read operations to accurately distinguish between different memory cell states without interference. The pre-charging action prepares the signal transmission path in advance, enabling multiple cells to share the bit line while minimizing signal interference during sequential read operations.
Data Source
AI summary
A semiconductor device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory cells. Each memory cell is coupled to a ground voltage node, a single bit line, and one of plural word lines for storing multi-bit data. The control circuit is configured to activate the plural word lines to read the multi-bit data stored in each memory cell.