Multi-bit Non-volatile SRAM Cell Design
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Solution Overview
Problem
Conventional non-volatile static random-access memory (nvSRAM) cells are limited to storing and recalling one databit per cell, which restricts their performance and data retention capabilities compared to multi-bit capabilities.
Innovation Solution
The implementation of a multi-bit non-volatile random access memory cell with a volatile storage element and a non-volatile storage circuit that includes multiple non-volatile storage elements, allowing selective connection via pass transistors for storing and recalling data, enabling the cell to store and recall two databits per cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional nvSRAM cells are used with a single non-volatile storage element, then the device complexity is low, but the data storage capacity is limited to one databit per cell
Solution Approach 1:
The non-volatile storage circuit is segmented into multiple independent non-volatile storage elements (first non-volatile storage element, second non-volatile storage element, etc.), each capable of storing one databit. This segmentation allows the cell to store multiple databits simultaneously while maintaining manageable complexity through modular architecture.
Solution Approach 2:
The pass transistors serve multiple functions: they act as selection switches for different non-volatile storage elements during store operations, and as connection switches during recall operations. This multi-functionality enables the same circuit components to support both store and recall operations for multiple databits, improving storage capacity without proportionally increasing device complexity.
2Reliability
If multiple non-volatile storage elements are connected to the volatile storage element, then the data retention and endurance are improved, but the device complexity increases
Solution Approach 1:
The non-volatile storage circuit is divided into multiple independent non-volatile storage elements, each contributing to data retention and endurance. This segmentation provides redundancy and reliability improvement while maintaining modular complexity that can be managed through systematic circuit design.
Solution Approach 2:
Multiple non-volatile storage elements are merged into a single non-volatile storage circuit that interfaces with the volatile storage element through shared pass transistors. This merging approach improves reliability through redundancy while consolidating control logic and reducing the overall complexity compared to having separate circuits for each storage element.
3Productivity
If dual data storage and recall operations are implemented, then the performance is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The cell is segmented into distinct functional blocks (volatile storage element, multiple non-volatile storage elements, pass transistors) that can be manufactured using standard CMOS processes. This segmentation allows for modular fabrication with well-established precision requirements for each component type.
Solution Approach 2:
The patent employs standard transistor parameters and voltage levels that are consistent with conventional CMOS manufacturing processes. By using parameter changes such as voltage control for the pass transistors and standard threshold voltages for the storage elements, the design achieves dual data storage and recall functionality without requiring exotic manufacturing precision.
Data Source
AI summary
Multi-bit non-volatile random access memory cells are disclosed. A multi-bit non-volatile random access memory cell may include a volatile storage element and a non-volatile storage circuit. The non-volatile storage circuit may include at least one first pass transistor connected to a data true (DT) node of the volatile storage element and at least one second pass transistor connected to a data complement (DC) node of the volatile storage element. The non-volatile storage circuit may also include multiple non-volatile storage elements. Each non-volatile storage element may be configured to be selectively connectable to the DT node of the volatile storage element via the at least one first pass transistor and selectively connectable to the DC node of the volatile storage element via the at least one second pass transistor, allowing the multi-bit non-volatile random access memory cell to store/recall more than one databit per cell.