Multi-bit Resistive-Switching Memory Cell with Independent Conduction Paths
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Solution Overview
Problem
Current resistive-switching nonvolatile random access memory (RRAM) technologies face challenges in integration with frontend manufacturing processes, leading to increased manufacturing costs and limitations in bit density due to their simple cell structure and limited operational capabilities.
Innovation Solution
A multi-bit resistive-switching memory cell and array design featuring multiple conduction paths with independent source and drain paths, utilizing a substrate, resistive-switching oxide layer, and gate electrode, allowing for high-resistance and low-resistance states, and employing specific voltage applications to set, reset, and read these states, thereby enhancing bit density and preventing cross-talk effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a simple metal-insulator-metal (MIM) configuration is used for RRAM, then the cell structure is simple and manufacturing is easier, but the device cannot be integrated to the frontend process, increasing manufacturing cost
Solution Approach 1:
The patent changes the material parameters and configuration of the RRAM device by using HfO2-based gate dielectrics and Ni gate electrodes in an MIS configuration instead of the traditional MIM structure. This parameter change enables the device to be integrated into frontend CMOS processes while maintaining resistive switching functionality, thus resolving the contradiction between manufacturing simplicity and integration capability
Solution Approach 2:
The patent employs composite material structures combining HfO2 dielectric layer with Ni gate electrodes and silicon substrate to create the MIS configuration. This composite approach enables both the resistive switching property and compatibility with standard CMOS fabrication processes, addressing the contradiction between simple structure and process integration
2Device complexity
If traditional single-bit RRAM cells are used, then the cell structure remains simple, but the bit density is limited
Solution Approach 1:
The patent segments the single conduction path into multiple independent conduction paths within the same memory cell structure. By creating separate source and drain conduction paths that can be independently controlled through word lines and bit lines, the cell achieves multi-bit storage capability without increasing the physical footprint, thus increasing bit density while maintaining structural simplicity
Solution Approach 2:
The patent transitions from single-bit to multi-bit storage by utilizing the dimensional capability of multiple conduction paths within the same cell. This allows the memory cell to store multiple bits of information simultaneously through different conduction paths, effectively increasing the information density without proportionally increasing the physical cell area
3Quantity of substance
If multiple conduction paths are implemented in a memory cell, then bit density increases, but cross-talk effects may occur between adjacent cells
Solution Approach 1:
The patent applies local quality control by enabling independent selection and control of different conduction paths through specific word line and bit line combinations. This allows the memory system to activate only the required conduction paths for reading or writing specific bits, minimizing interference and cross-talk between adjacent cells while maintaining high bit density
Solution Approach 2:
The patent uses word lines and bit lines as intermediary control elements that selectively activate specific conduction paths. These intermediaries enable precise control over which conduction paths are active during read/write operations, preventing unwanted current flow and cross-talk between adjacent memory cells while maintaining multi-bit storage capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient multi-bit storage with independent control of conduction paths, increasing bit density and preventing cross-talk errors, thus improving the operational efficiency and manufacturing feasibility of RRAM arrays.
Implementation Method 1
each conduction path can be in high-resistance state (HRS) or low-resistance state (LRS)... set voltage (VSET) or reset voltage (VRESET) can be applied on the source and drain to set or reset the state of the source and drain conduction path
Implementation Method 2
when a gate voltage, less than a threshold voltage, is applied on the gate to cut the conduction channel off
Data Source
AI summary
This invention proposes a multi-bit resistive-switching memory cell and array thereof. Multiple conduction paths are formed on each memory cell and independent of each other, and each conduction path can be in a high-resistance or low-resistance state, so as to form a multi-bit resistive-switching memory cell. A memory cell array can be formed by arranging a plurality of multi-bit resistive-switching memory cells, and the memory cell array provides a simple, high density, high performance and cost-efficient proposal.