Multi-Chip Clock Synchronization Using TDC Phase Measurement
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Solution Overview
Problem
In complex electronic systems, especially in MIMO radar systems and autonomous driving vehicles, synchronization of clock signals among multiple integrated circuits (ICs) is crucial for proper functioning, but existing methods often introduce errors and inefficiencies, affecting system performance.
Innovation Solution
A distributed local oscillator is shared among multiple ICs, with a time-to-digital converter (TDC) measuring phase or latency differences between clock signals, and a synchronization clock generator synchronizing internal clock signals with a master clock signal, using a controller to adjust and maintain coherence across the ICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple ICs use independent clock signals, then each IC operates independently, but synchronization errors occur affecting system performance
Solution Approach 1:
The patent merges multiple independent clock sources into a single shared clock signal that is distributed to all ICs. This consolidation ensures that all ICs operate from the same clock reference, eliminating synchronization errors while reducing the overall complexity of managing multiple independent clock distributions.
Solution Approach 2:
The patent introduces a clock synchronization intermediary that mediates between the master clock source and individual ICs. This intermediary component coordinates timing across all ICs, ensuring synchronized operation without requiring complex point-to-point clock distribution paths between each IC pair.
2Reliability
If a shared clock signal is used among multiple ICs, then synchronization is improved, but clock signal distribution complexity increases
Solution Approach 1:
The patent segments the clock distribution network into hierarchical levels, with a master clock source at the top level and distributed clock buffers at lower levels. This segmentation allows the shared clock signal to be managed in manageable segments, reducing the complexity of the overall distribution network while maintaining synchronization across all ICs.
Solution Approach 2:
The patent designs the shared clock distribution network to serve multiple functions simultaneously: it provides timing synchronization, signal distribution, and system coordination. This multi-functionality reduces the need for separate dedicated components, thereby reducing overall distribution network complexity while maintaining reliable clock synchronization.
3Measurement precision
If clock signals are not synchronized, then system operation is simpler, but measurement precision and processing gain deteriorate
Solution Approach 1:
The patent implements a feedback mechanism where the actual clock phases at each IC are monitored and compared against the master clock reference. This feedback information is used to adjust and correct any phase deviations, thereby improving measurement precision for phase difference calculations while maintaining the processing gain benefits of synchronized operation across all ICs.
Data Source
AI summary
An EC platform including a controller to control multiple integrated circuits (ICs) to synchronize an operational internal clock signal of an IC with a master clock signal. The controller generates commands for the IC to measure a phase difference or latency difference between an initial internal clock signal of the IC and an input clock signal to the IC from a parent IC. The controller further receives a difference signal from the IC to indicate the phase or latency difference. The IC includes a measurement circuit to measure the phase or latency difference, and to generate a difference signal to indicate the phase or latency difference. The IC further includes a synchronization clock generator to generate, based on the initial internal clock signal and the difference signal, an operational internal clock signal synchronized with the master clock signal. Other embodiments may also be described and claimed.