Multi-Chip Fan-Out Package Layout for Warpage and Signal Paths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current fan-out semiconductor packages face challenges in miniaturization and warpage issues when multiple semiconductor chips are used, with limitations in thermal and electrical performance due to the use of printed circuit boards and wire bonding methods.
Innovation Solution
A fan-out semiconductor package design that includes a first and second connection structure with redistribution layers, metal members for signal and warpage control, and encapsulants to cover semiconductor chips and metal members, allowing for efficient electrical connection and reduced warpage through the use of multiple semiconductor chips without a printed circuit board.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple semiconductor chips are used in a fan-out package, then functionality and performance are improved, but warpage occurs due to thermal expansion differences
Solution Approach 1:
The patent introduces a specific structural configuration with metal members having controlled thickness (5-20 micrometers) and area ratios (10-30%) to adjust the thermal expansion parameters of the package, thereby compensating for warpage while maintaining enhanced performance from multiple chips
Solution Approach 2:
The patent employs a composite structure combining semiconductor chips, encapsulants, and metal members with different material properties. This composite architecture balances thermal expansion characteristics across layers, reducing warpage while preserving the functional benefits of multi-chip integration
2Reliability
If wire bonding and printed circuit boards are used, then electrical connection is achieved, but device size and complexity increase
Solution Approach 1:
The patent extracts and eliminates the printed circuit board from the package structure, directly mounting semiconductor chips on the substrate. This removal of the intermediate PCB layer simplifies the overall device structure while maintaining reliable electrical connections through direct chip-to-substrate bonding
Solution Approach 2:
The patent merges the functions of the printed circuit board, wire bonding, and interconnection into a single integrated substrate structure with redistribution layers. This consolidation eliminates multiple separate components and processes, reducing device complexity while preserving electrical connectivity
Data Source
AI summary
A fan-out semiconductor package includes a first connection structure having first and second surfaces, a first semiconductor chip disposed on the first surface, a first encapsulant disposed on the first surface and covering at least a portion of the first semiconductor chip, a second semiconductor chip disposed on the second surface, one or more first metal members disposed on the second surface, one or more second metal members disposed on the second surface, a second encapsulant disposed on the second surface and respectively covering at least portions of the second semiconductor chip and the first and second metal members, and a second connection structure disposed on an opposite side of a side of the second encapsulant, on which the first connection structure is disposed.