Multichip Module Fabrication Using PCB Traces
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Solution Overview
Problem
Current high frequency multichip modules are expensive and labor-intensive to produce due to the use of exotic substrates and methods like wire bonding and soldering, which lead to parasitic losses, variability, and reliability issues.
Innovation Solution
A method for fabricating high performance, affordable high frequency multichip modules using a tiled and stacked approach with an interconnect assembly that includes electronic die, a thermal management layer, and controlled impedance interconnects, leveraging existing technologies and packaging techniques to reduce costs and improve reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If exotic substrates like LTCC are used for high frequency modules, then high frequency performance is achieved, but manufacturing cost and complexity increase significantly
Solution Approach 1:
The patent changes the substrate material parameters from exotic LTCC to standard organic substrates, and changes the interconnect parameters from wire bonds to printed circuit board traces. This parameter substitution maintains high frequency performance while dramatically reducing manufacturing complexity and cost.
Solution Approach 2:
The patent replaces expensive, difficult-to-manufacture LTCC substrates with inexpensive, easily manufactured organic PCB substrates. This substitution uses readily available, low-cost materials that can be mass-produced using standard PCB fabrication processes.
2Reliability
If wire bonding is used to interconnect RF chips, then electrical connection is achieved, but parasitic losses and variability increase
Solution Approach 1:
The patent replaces the mechanical wire bonding process with a printed circuit board trace interconnection system. This substitution eliminates the mechanical wire bonds that cause parasitic losses and variability, replacing them with integrated PCB traces that provide consistent, low-parasitic electrical connections.
3Strength
If soldering is used to attach chips to substrate, then mechanical attachment is achieved, but flux contamination and reliability issues occur
Solution Approach 1:
The patent extracts and eliminates the soldering process entirely from the assembly method. By designing the module so that RF chips are interconnected via PCB traces without requiring solder attachment, the harmful flux contamination and associated reliability issues are completely removed while maintaining mechanical stability through the PCB structure.
4Ease of manufacture
If thick gold bond pads are used on RF chips, then solder attachment is enabled, but solder/gold embrittlement occurs degrading reliability
Solution Approach 1:
The patent extracts and eliminates the need for thick gold bond pads by removing the solder attachment process entirely. The RF chips are interconnected through PCB traces that connect to pad structures on the substrate, eliminating the solder/gold embrittlement mechanism while maintaining electrical and mechanical connectivity.
5Quantity of substance
If stacked integrated circuit packages are used, then circuit density is increased, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the module into a layered structure with RF chips stacked above the PCB substrate. This segmentation allows each layer to be manufactured and tested independently, then assembled together. The PCB substrate provides a stable, precision-manufactured base that simplifies alignment requirements for the stacked components.
Data Source
AI summary
An interconnect assembly for use in high frequency applications includes an interconnect structure, a plurality of electronic die disposed on the interconnect structure, and an encapsulant at least partially surrounding the plurality of electronic die. The interconnect structure includes a plurality of layers. The interconnect assembly further includes a thermal management layer disposed within a portion of the encapsulant and proximate to the plurality of electronic die and a controlled impedance interconnect connected to the interconnect structure and extending to a peripheral surface of the interconnect assembly.