Multi-chip Package Single Lead Addressing
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Solution Overview
Problem
Multi-chip packages face challenges in reducing size and complexity due to the need for multiple pads and leads to select and address individual chips, limiting flexibility in packaging and increasing material usage for wiring.
Innovation Solution
A multi-chip package design utilizing a single lead and pad circuits with control circuits to provide chip address signals, allowing each chip to be identified and operated using a single lead, reducing the number of pads and leads required, and enabling stable voltage stabilization for chip selection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple pads and leads are used to select and address individual chips in a multi-chip package, then chip selection capability is improved, but package size and wiring complexity increase
Solution Approach 1:
The single lead is designed to serve multiple functions: it provides both power supply voltage to the pad circuits and carries address signals for chip selection. This multi-functional design eliminates the need for separate dedicated address leads, reducing overall package complexity while maintaining full chip selection capability across multiple chips.
Solution Approach 2:
The pad circuits utilize voltage level changes on the single lead to encode address information. By interpreting different voltage states (presence or absence of power supply voltage) as binary address bits, the system transforms a single physical lead into a multi-bit address bus, enabling chip selection without increasing physical lead count.
2Measurement precision
If multiple pads are used for chip addressing, then accurate chip identification is improved, but material usage for wiring increases
Solution Approach 1:
The invention merges the power supply function and address signal function into a single lead. The pad circuits are designed to detect the presence or absence of power supply voltage on this combined lead, interpreting these states as address information. This consolidation eliminates multiple separate address leads, reducing wiring material while preserving precise chip identification through voltage-based address encoding.
3Device complexity
If a single lead is used for power and address signals, then package size is reduced, but voltage stabilization for chip selection becomes more difficult
Solution Approach 1:
The pad circuit is segmented into distinct functional blocks: a control circuit that stabilizes the voltage to appropriate logic levels, an ESD circuit that protects against voltage spikes, and address node circuitry that interprets the stabilized voltage. This segmentation allows the circuit to reliably extract address information from the single lead's voltage variations while maintaining stable operation despite the lead's dual function.
Solution Approach 2:
The ESD (electrostatic discharge) circuit is incorporated to protect against sudden voltage increases or spikes on the single lead before they can damage sensitive address decoding circuitry. This protective circuitry pre-cushions the system against voltage transients, ensuring reliable operation of the chip selection mechanism despite the challenging single-lead interface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the size and complexity of multi-chip packages, allows for more flexible chip arrangement, and stabilizes chip operations by using a single lead for power and address signals, minimizing material usage and ensuring accurate chip selection.
Implementation Method 1
a control circuit electrically coupled to the pad and configured to stabilize a voltage of the pad to an addressing voltage so as to provide the chip address signal
Implementation Method 2
an electrostatic discharge (ESD) circuit coupled to and disposed between the address node and the logic element and configured to prevent the voltage of the address node from suddenly increasing
Data Source
AI summary
A multi-chip package includes a single lead and a plurality of inner package chips. Each of the plurality of inner package chips includes at least one pad circuit and an internal circuit. The pad circuit is selectively coupled to the lead and configured to provide a chip address signal corresponding to a connection state to the lead. The inner package chip receives the chip address signal to identify a corresponding inner package chip.