Multi-Chip Package Layout Without Interposer or TSVs

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Solution Overview

Problem

The complexity and cost of fabricating Through-Silicon Vias (TSV) in interposer layers for multi-chip packages are significant, making the integration process expensive and inefficient.

Innovation Solution

A method for manufacturing a chip package that eliminates the need for an interposer layer and TSVs by using a support carrier with conductive bumps and an interconnection device, allowing direct electrical connection between chips and external devices without TSVs, thereby simplifying the integration process and reducing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an interposer layer with Through-Silicon Vias (TSV) is used to connect chips, then electrical connection between chips and external devices is achieved, but the manufacturing area increases and fabrication complexity increases leading to higher cost

Engineering Contradiction:

Improveelectrical connectionVSAvoidfabrication complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and removes the interposer layer from the package structure, eliminating the need for TSV fabrication. The support carrier directly provides mounting surfaces and conductive paths, removing the complex intermediate layer while maintaining electrical connectivity functions.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The support carrier is designed to perform multiple functions: providing mechanical support, enabling chip mounting, establishing electrical connections through conductive bumps, and facilitating heat dissipation. This multi-functional design replaces the specialized interposer layer, reducing overall device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If an interposer layer with Through-Silicon Vias (TSV) is used to connect chips, then electrical connection between chips and external devices is achieved, but manufacturing cost increases

Engineering Contradiction:

Improveelectrical connectionVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The support carrier uses cost-effective materials and simpler fabrication processes compared to precision TSV manufacturing. The conductive bumps and redistribution layers are formed using standard semiconductor processes, avoiding the expensive and time-consuming TSV fabrication steps.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent changes the structural parameters by eliminating the thick interposer layer and replacing it with a thinner support carrier structure. The conductive paths are modified from vertical TSVs to lateral conductive bumps and redistribution layers, fundamentally changing the connection architecture to reduce manufacturing cost.

Inventive Principle:

Principle #35Parameter changes

3Adaptability or versatility

If an interposer layer is used, then chip integration is achieved, but the area of the package increases

Engineering Contradiction:

Improvechip integrationVSAvoidpackage area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent transitions from a vertical stacking approach with thick interposer layers to a more planar integration scheme using conductive bumps and redistribution layers. This dimensional reorganization allows chips to be integrated with reduced vertical height and smaller overall package footprint.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces manufacturing costs and simplifies the integration process by enabling direct electrical connections between chips and external devices without the need for TSVs, while maintaining reliable chip-to-chip and chip-to-device connectivity.

Implementation Method 1

the active side of each chip is connected to a respective subset of the first conductive bumps and a respective subset of the second conductive bumps

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

Forming a photoresist layer with a through hole pattern on the surface of one side of the seed layer that is facing away from the first support carrier; wherein the through hole pattern includes through holes penetrating the photoresist layer

Methodology Applied

Scientific EffectPhotolithography: Photography

Data Source

PatentUS20240387500A1Multi-chip package and method of making

Publication Date: 2024.11.21 SHANGHAI YIBU SEMICON CO LTD

AI summary

The present disclosure relates to a multi-chip package and a method of manufacturing the same. The method comprises providing a first support carrier, and forming first conductive bumps and an interconnection device on a surface on one side of the first support carrier. The interconnection device has a passive side attached to the first support carrier and an opposing active side provided with second conductive bumps. The method further comprises connecting an active side of each chip of at least two chips to a respective subset of the first conductive bumps and a respective subset of the second conductive bumps. Thus, the chips can be electrically connected to an external device through the first conductive bumps, and electrically connected to each other through the second conductive bumps, without an interposer layer or Through-Silicon Vias (TSV), thereby reducing the manufacturing cost and simplifying the chip package integration process.