Multichip Ray Tracing With Divided Acceleration Structures
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Solution Overview
Problem
Existing 3D graphics processing technologies face challenges in efficiently sharing acceleration structures for traversal & intersection test (T&I) operations across multiple chips during ray tracing, leading to increased computation and memory bandwidth requirements.
Innovation Solution
A multichip ray tracing device and method that divides acceleration structures among multiple memory units and ray tracing core units, allowing for internal and external ray tracing operations to be performed independently and efficiently across chips, with each unit sharing and exchanging ray information as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If acceleration structures are shared among multiple chips during ray tracing operations, then computational efficiency is improved, but memory bandwidth requirements and system complexity increase
Solution Approach 1:
The acceleration structure is divided into multiple divided acceleration structures, with each chip receiving a specific portion. This segmentation allows parallel processing across multiple chips while maintaining manageable data structures, resolving the contradiction by enabling efficient computation without requiring all chips to access the entire acceleration structure simultaneously.
Solution Approach 2:
The patent introduces a hierarchical dimension to acceleration structure access by creating divided acceleration structures that can be selectively accessed. This dimensional organization allows chips to first access local divided structures and only access global structures when necessary, reducing memory bandwidth requirements while maintaining computational efficiency.
2Quantity of substance
If acceleration structures are divided and distributed across multiple memory units, then memory bandwidth requirements are reduced, but access time to data nodes may increase
Solution Approach 1:
Each chip is assigned specific divided acceleration structures stored in corresponding memory units, creating localized data access patterns. This local quality principle reduces memory bandwidth requirements by eliminating redundant accesses to distant memory units, while the hierarchical structure ensures that frequently accessed data remains locally available.
Solution Approach 2:
The acceleration structure is pre-divided and distributed to appropriate memory units before ray tracing operations begin. This preliminary organization allows chips to directly access their assigned divided acceleration structures without dynamic allocation overhead, reducing access time while maintaining reduced memory bandwidth requirements.
3Productivity
If ray tracing operations are performed independently on divided acceleration structures, then parallel processing efficiency is improved, but coordination overhead between chips increases
Solution Approach 1:
The ray tracing workload is segmented by dividing the acceleration structure into separate portions assigned to different chips. Each chip independently processes rays against its assigned divided acceleration structure, maximizing parallel processing efficiency. The segmentation is designed to minimize coordination requirements by clearly defining data ownership boundaries.
Solution Approach 2:
The patent introduces a coordination mechanism that acts as an intermediary for inter-chip communication when rays need to access data nodes outside their local divided acceleration structure. This intermediary layer manages the complexity of coordination while allowing independent processing to continue, resolving the contradiction by abstracting coordination overhead.
Data Source
AI summary
The present disclosure relates to a multichip ray tracing device and method, wherein the device includes a plurality of memory units; an acceleration structure division processing unit that divides an acceleration structure (AS) into a plurality of divided acceleration structures and stores each of the plurality of divided acceleration structures in a corresponding memory unit among the plurality of memory units; and a plurality of ray tracing core units connected to the plurality of memory units, wherein each of the plurality of ray tracing core units performs an internal ray tracing (Internal RT) operation for a corresponding divided acceleration structure and transmits corresponding ray information to a corresponding ray tracing core unit to perform an external ray tracing (External RT) operation when attempting to access a data node that is not in the corresponding divided acceleration structure in the process of the internal ray tracing operation.