Multichip Stacking Package Interlaced Reciprocation Stacking
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Solution Overview
Problem
Conventional multichip package structures face issues with chip cracking during wire bonding due to insufficient support, requiring increased chip thickness which complicates material preparation and production control.
Innovation Solution
A multichip stacking package structure that uses an interlaced reciprocation stacking method with spacers positioned between chips to alter wire bonding points, providing optimal support and avoiding chip cracking without wire bonding on spacers, thus maintaining uniform chip thickness and simplifying production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chip thickness is increased to provide sufficient support during wire bonding, then chip cracking risk is reduced, but material preparation complexity and production control difficulty increase
Solution Approach 1:
The patent divides the support function into two parts: the chip itself and an additional support structure (such as a support chip or extended substrate). This segmentation allows the main chip to maintain its original thin profile while the separate support structure provides the necessary mechanical strength during wire bonding, thus resolving the contradiction between chip thickness and support adequacy.
Solution Approach 2:
The patent introduces an intermediary support structure that acts as a mediator between the thin chip and the bonding process. This support structure absorbs the mechanical stress during wire bonding, protecting the chip from cracking while allowing the chip to remain thin, thereby eliminating the need to increase chip thickness.
2Strength
If chip thickness is increased to satisfy stress during wire bonding, then chip damages are avoided, but production process complexity increases
Solution Approach 1:
The support function is segmented from the chip structure, allowing the chip to be manufactured at optimal thin thickness while the separate support structure handles the mechanical stress requirements. This simplifies production by allowing independent optimization of chip fabrication and support structure fabrication processes.
Solution Approach 2:
Instead of making the chip thicker to provide support, the patent inverts the approach by adding a support structure underneath or alongside the chip. This inversion allows the chip to remain thin and easy to manufacture while still achieving the necessary stress resistance during bonding.
3Reliability
If interlaced reciprocation stacking is used with spacers, then wire bonding position is optimized and chip cracking is reduced, but package structure complexity increases
Solution Approach 1:
The spacer acts as an intermediary element that facilitates the interlaced reciprocation stacking arrangement. It provides the necessary spacing and positioning to enable wire bonding at optimal locations while preventing direct contact between adjacent chips that could cause cracking. The spacer's simple geometric form keeps the added complexity minimal while achieving the reliability benefits.
Solution Approach 2:
The patent utilizes the vertical dimension by stacking chips in an interlaced reciprocation pattern with spacers, rather than arranging them in a simple planar configuration. This dimensional approach allows wire bonding to be performed at optimized positions on different levels, improving bonding reliability while the regular stacking pattern keeps the overall structure manageable.
Data Source
AI summary
The present invention relates to a multichip stacking package structure and a method for manufacturing the same, wherein the multichip stacking package structure comprises a substrate including a plurality of electrical connecting pad; a first chip with a lower surface stacked on the substrate; a second chip stacked on an upper surface of the first chip by a interlaced reciprocation stacking way; a spacer stacked on an upper surface of the second chip by the interlaced reciprocation stacking way; and third chip stacked on the an upper surface of the spacer by the interlaced reciprocation stacking way, so that a first spacing is formed between an end of the third and an end of the spacer. Thereby, a position of a stress point is changed to reduce a risk of the chip crack during wire bonding.