Multi-Core BIST Testing via Segmented Debug Ports
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Solution Overview
Problem
Existing multi-core integrated circuits require lengthy and costly testing processes due to the need for sequential testing of BIST engines with different architectures, and lack secure access mechanisms, making concurrent testing of memory blocks across multiple cores inefficient and potentially damaging.
Innovation Solution
A multi-core integrated circuit design that includes a control circuit to configure TAP controllers in a predetermined test mode, allowing concurrent initiation of BIST engines and secure debug access through a debug access module with authentication, enabling simultaneous testing of memory blocks with different architectures while preventing unauthorized access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential testing of BIST engines with different architectures is performed, then secure access to each core is maintained, but testing time increases significantly
Solution Approach 1:
The system segments BIST engines into two categories: homogeneous engines (same architecture) and heterogeneous engines (different architectures). Homogeneous engines are tested concurrently through a single debug port, while heterogeneous engines are tested sequentially through different debug ports. This segmentation allows maximum parallelization without compromising security or test accuracy.
Solution Approach 2:
Multiple debug ports are provided, each capable of testing multiple types of BIST engines. The debug ports are designed with universal functionality to handle both homogeneous and heterogeneous engine testing, allowing flexible configuration and concurrent operation when appropriate.
2Loss of time
If concurrent testing of BIST engines with different architectures is attempted, then testing time is reduced, but access security and hardware protection are compromised
Solution Approach 1:
The system provides separate debug ports for different engine types to enable concurrent testing while maintaining security. Each debug port is configured with appropriate access controls and authentication mechanisms specific to the engine architecture it tests, preventing unauthorized cross-access.
Solution Approach 2:
Authentication mechanisms and control circuits act as intermediaries between the debug ports and BIST engines. These intermediaries verify credentials, enforce access policies, and manage the testing process securely, allowing concurrent operations without direct unauthenticated access to hardware elements.
3Productivity
If multiple debug ports are provided for concurrent testing, then testing efficiency improves, but device complexity increases
Solution Approach 1:
Multiple debug ports are designed with similar functional capabilities and interfaces, allowing them to be used in a uniform manner despite their multiplicity. Each port can test multiple engine types and follows consistent protocols, reducing the operational complexity despite the increased hardware count.
Solution Approach 2:
The system dynamically configures which debug ports are active and how they are connected to BIST engines based on the testing requirements. Control circuits enable flexible routing and configuration, allowing the system to adapt to different test scenarios without requiring permanent complex wiring for all possible configurations.
4Measurement precision
If BIST engines with different architectures are tested one at a time, then test accuracy is maintained, but overall memory testing time increases
Solution Approach 1:
The test suite is segmented into phases: homogeneous engine tests run concurrently to maximize throughput, while heterogeneous engine tests are scheduled sequentially to ensure accuracy. This segmentation allows the system to optimize for both speed and precision depending on the engine type being tested.
Solution Approach 2:
While one set of engines is being tested, the system prepares test configurations and stimuli for the next set of engines. Control circuits continuously manage the testing flow, ensuring that no time is wasted between test sequences and that each engine receives appropriate test inputs without interruption.
Data Source
AI summary
A multi-core integrated circuit includes first and second sets of processor cores and corresponding first and second test access ports (TAPs). The first and second TAPs are connected to corresponding first and second debug ports by way of corresponding first and second TAP controllers. The first and second sets of processor cores include first and second memory blocks and corresponding first and second built-in-self-testing (BIST) engines of different architectures. A control circuit configures the first and second TAP controllers and the connection between the first and second sets of processor cores and the first and second debug ports, for initiating the first and second BIST engines for testing the memory blocks using a predetermined test mode. A debug access module provides secure access to the first and second debug ports.