Multicore Chip Place and Route via Symmetric Regionalization
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Solution Overview
Problem
Current multicore chip integration methods, whether hierarchical or flat, face challenges in design flexibility and efficiency due to large superclusters or whole-chip considerations, leading to increased time and expense in achieving performance specifications.
Innovation Solution
The method involves laying out virtual regionalization lines to create symmetric regions on a chip, designating one as a master region and others as duplicates, placing recurring functional blocks and wires symmetrically across these regions, allowing for efficient replication and reduced design verification efforts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a hierarchical approach is used to integrate multiple cores into superclusters, then chip integration is simplified, but the supercluster dimension becomes large which limits chip floorplan options and makes design changes difficult
Solution Approach 1:
The patent applies segmentation by dividing the chip into multiple identical regions, each containing a core and surrounding logic. This allows the chip to be viewed as a collection of smaller, manageable units rather than a single large supercluster, thereby maintaining integration simplicity while significantly increasing floorplan flexibility and design adaptability.
2Device complexity
If all cores and functional logics are placed and routed at the chip level in a flat approach, then hierarchical boundaries are avoided, but the entire chip must be considered as a whole which increases time and expense for routing, timing, and design verification
Solution Approach 1:
The patent segments the chip into identical regions that can be independently placed and routed. This eliminates the need to treat the entire chip as a single complex unit, thereby reducing the time and expense for routing, timing analysis, and design verification while avoiding hierarchical boundaries.
Solution Approach 2:
The patent employs copying by creating multiple identical regions from a single template. Once one region is designed and verified, the same design can be copied to other regions, significantly reducing the overall design time and verification effort compared to designing each region independently at the chip level.
3Reliability
If the chip is considered as a whole during place and route process, then overall routing and timing can be optimized, but the time and expense required to converge the chip to a final design increases
Solution Approach 1:
The patent divides the chip into identical regions that can be independently optimized for routing and timing. This segmentation allows for faster local optimization while maintaining overall chip performance, thereby improving design convergence speed without sacrificing routing and timing quality.
Solution Approach 2:
The patent combines the benefits of local optimization (by treating each region independently) with global optimization (by ensuring all regions are identical and properly interconnected). This merging approach achieves overall routing and timing optimization while significantly reducing design convergence time compared to treating the entire chip as a single unit.
Data Source
AI summary
A number of virtual regionalization lines are laid out across a chip such that the virtual regionalization lines delineate a plurality of regions on the chip. One of the plurality of regions on the chip is designated as a master region and each of a remainder of the plurality of regions on the chip is designated as a duplicate region. A number of functional blocks are placed in the master region. Each of the functional blocks is replicated in each duplicate region by placing each functional block in each duplicate region so as to be symmetric with the corresponding functional block in the master region about the virtual regionalization lines. Wires are routed in the master region. The wires routed in the master region are replicated in each duplicate region so as to be symmetric about the virtual regionalization lines.