Multicore Chip Test Architecture for Parallel Core Verification
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Solution Overview
Problem
The increasing complexity of semiconductor chips with multiple cores poses a challenge in efficient testing, as conventional methods result in substantial increases in test time and required Input/Output pins, making it inefficient to test circuits with a plurality of substantially similar cores.
Innovation Solution
An integrated circuit chip architecture that allows for simultaneous testing of multiple cores using a shared test input and comparator circuitry to detect mismatches between test result data and expected results, with mismatch indications stored in memory, thereby reducing test time and maintaining a constant number of input/output pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional testing methods are used for each core separately, then testing completeness is improved, but test time increases substantially
Solution Approach 1:
The patent combines multiple separate testing operations into a single integrated testing process. Multiple cores are tested simultaneously by applying test patterns once and capturing responses from all cores through shared I/O pins, rather than testing each core separately. This merging of testing operations maintains comprehensive testing coverage while dramatically reducing the total test time required.
Solution Approach 2:
The patent implements universal testing resources that serve multiple cores. A single set of I/O pins and test pattern generation circuitry is designed to test multiple cores simultaneously. The test patterns and response capture mechanisms are made multi-functional, allowing the same hardware resources to efficiently test any combination of cores on the chip, thereby reducing both test time and the number of required I/O pins.
2Reliability
If conventional testing methods are used for each core separately, then testing completeness is improved, but the number of required Input/Output pins increases
Solution Approach 1:
The patent merges the I/O pin requirements for testing multiple cores into a shared set of pins. Instead of allocating dedicated I/O pins to each core for test pattern application and response capture, the system combines these functions so that a single set of pins can serve multiple cores simultaneously through multiplexing and time-division techniques, thereby maintaining testing completeness while reducing the total pin count.
Solution Approach 2:
The test I/O interface is designed with universal, multi-functional capabilities that allow the same pins to be dynamically allocated to different cores during the testing process. The test pattern generation and response capture circuitry are made versatile to handle multiple cores through a single interface, eliminating the need for dedicated pins per core and reducing overall device complexity.
3Adaptability or versatility
If multiple separate test inputs and outputs are provided for each core, then individual core testing capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the testing functionality into modular components that can be selectively activated for different cores. The test pattern generation, distribution, and response capture are divided into functional segments that can be independently configured for each core while sharing common infrastructure. This segmentation allows individual core testing capability to be maintained through selective activation without requiring complete separate testing paths for each core, thereby reducing overall device complexity.
Solution Approach 2:
The patent introduces intermediary circuitry that mediates between the test inputs/outputs and multiple cores. Instead of direct connections from each test input/output to each core, intermediary multiplexers, switches, and distribution networks are inserted to manage the connections dynamically. These intermediaries enable individual core testing capability while consolidating the physical I/O interfaces, thereby reducing device complexity.
Data Source
AI summary
An integrated chip architecture is provided which allows for efficiently testing multiple cores included in the integrated chip architecture. In particular, the provided approach enables the test time and the number of required Input/Output test pins is nearly independent from the number of cores included in the multicore chip. The presented embodiments provide a multicore chip architecture which allows for providing input data to the multiple cores in parallel for simultaneously testing the multiple cores, and analyzing the resulting multiple test outputs on chip. As a result of this analysis embodiments may store on chip an indication for those cores that have not successfully passed the test.