Multi-Core Clock Management for Per-Core Frequency Switching
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Solution Overview
Problem
Multi-core processors face limitations in optimizing performance and power consumption due to all processor cores operating within the same clock domain, which restricts independent frequency adjustments and synchronization with function blocks.
Innovation Solution
A clock management circuit that generates distinct core clock signals and an interface clock signal by selecting between two frequencies, allowing independent frequency adjustments for each processor core and synchronizing communication, while simultaneously deactivating clock signals during frequency changes to prevent errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If all processor cores operate within the same clock domain using the same clock signal, then system simplicity is maintained, but performance optimization and power consumption efficiency are limited
Solution Approach 1:
The patent divides the unified clock domain into multiple independent clock domains, with each processor core assigned to its own clock domain. This segmentation allows each core to operate with independently adjustable clock signals, enabling differentiated frequency control for performance optimization while maintaining manageable system complexity through modular clock management.
Solution Approach 2:
The patent implements dynamic clock frequency adjustment for each processor core through separate clock management circuits. Each core can dynamically change its operating frequency based on workload requirements, transitioning between different clock domains as needed. This dynamic capability enables real-time performance optimization without requiring system-wide frequency changes.
2Productivity
If clock frequency is changed to optimize performance, then processing speed improves, but operation errors may occur due to synchronization issues
Solution Approach 1:
The patent activates a clock gating signal before changing the clock frequency to prevent operation errors. The gating signal is prepared in advance and applied to the processor core during the frequency transition period, ensuring that no erroneous operations occur while the clock signal is being switched between different frequency domains. This preliminary protective action maintains reliability during performance optimization transitions.
Solution Approach 2:
The patent introduces a clock gating signal as an intermediary mechanism between the clock frequency change and the processor core operation. This gating signal acts as a mediator that controls the timing and transition of clock signals, ensuring smooth frequency changes without causing synchronization errors or operational failures in the processor core.
3Adaptability or versatility
If independent frequency control per core is implemented, then performance optimization is improved, but clock management complexity increases
Solution Approach 1:
The patent designs the clock management circuit with multi-functional capabilities that handle multiple processor cores through standardized interfaces and control mechanisms. The clock management system can serve multiple cores simultaneously, providing independent frequency control to each core while using shared control logic and gating mechanisms. This universal approach reduces the overall complexity compared to having separate dedicated clock management for each core.
Data Source
AI summary
A multi-core system includes a multi-core processor, a function block, a clock management circuit, and a control circuit. The multi-core processor includes a plurality of processor cores configured to operate based on a plurality of core clock signals, respectively. The function block communicates with the multi-core processor based on an interface clock signal. The clock management circuit generates each of the plurality of core clock signals by selecting one of a first clock signal having a first frequency and a second clock signal having a second frequency different from the first frequency based on each of a plurality of frequency selection signals. The clock management circuit generates the interface clock signal based on the second clock signal. A control circuit may generate the plurality of frequency selection signals corresponding to the plurality of processor cores, respectively.