Multicore 3D Graphics Memory Layout for Ordered Tile Rendering
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Solution Overview
Problem
Implementing rendering tasks in parallel on a multicore GPU while maintaining the order of primitives as provided by the application driver and managing memory efficiently to facilitate the rendering of complex scenes.
Innovation Solution
A multicore graphics rendering system with a hierarchical memory management system that uses allocation lists and virtualised memory spaces to manage memory allocation and ordering of rendering tasks, ensuring efficient parallel processing of geometry and fragment processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If rendering tasks are processed in parallel on multicore GPU, then rendering speed is improved, but maintaining the order of primitives becomes difficult
Solution Approach 1:
The patent applies preliminary action by pre-assigning group indices to groups of primitives before parallel processing begins. This ordering information is stored and used during fragment processing to ensure that even though geometry processing occurs in parallel without strict ordering, the final rendering maintains the correct primitive sequence. The group indices are established in advance and used as reference markers throughout the rendering pipeline.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of an allocation list that tracks memory allocations associated with specific group indices and frame portions. This allocation list acts as a mediator between the parallel geometry processing stage and the sequential fragment processing stage, ensuring that memory is allocated and freed in the correct order while allowing parallel execution. The intermediary structure decouples the parallel processing from the ordering requirements.
2Adaptability or versatility
If memory is allocated for complex scenes, then rendering capability is improved, but memory overflow becomes more likely
Solution Approach 1:
The patent implements dynamic memory management where memory allocations are tracked and released based on completion status rather than being statically allocated for the entire scene. The system dynamically adjusts memory usage by freeing portions of memory associated with completed frame portions while retaining allocations for incomplete portions. This allows the system to handle complex scenes adaptively without requiring excessive peak memory allocation.
Solution Approach 2:
The patent applies discarding and recovering by systematically freeing memory allocations once their associated frame portions are completely processed. The allocation list tracks which memory portions are no longer needed and enables their release back to the memory pool. This continuous recovery of memory resources allows the system to maintain high rendering capability for complex scenes while preventing memory overflow through efficient resource reuse.
3Productivity
If parallel processing is implemented, then rendering efficiency is improved, but memory management complexity increases
Solution Approach 1:
The patent segments memory management into distinct tracked portions, each associated with specific frame portions and group indices. Rather than managing memory as a single undifferentiated resource, the system divides memory allocations into discrete segments that can be independently tracked, allocated, and freed. This segmentation simplifies the management complexity by creating manageable units with clear ownership and lifecycle information stored in the allocation list.
Data Source
AI summary
A multicore graphics rendering system includes a plurality of cores configured to implement tile-based rendering of a stream of primitives. First cores are configured to process groups of primitives, to produce transformed geometry data. The graphics rendering system uses at least one virtualised memory space. At least one virtualised memory space is segmented such that the first cores are allocated respective non-overlapping virtual address ranges in the space, the virtual address ranges being associated with different entries in a top level of the index. The top level of the hierarchical index is pre-allocated, and each core is primed by providing it with said top level of the hierarchical index.