Multi-Die Semiconductor Packaging With Active and Dummy Through Vias
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Solution Overview
Problem
The semiconductor industry faces challenges in integrating multiple electronic components with shrinking feature sizes and the need for more creative packaging techniques to enhance integration density and performance.
Innovation Solution
The formation of a die structure comprising integrated circuit dies, active through vias, and dummy through vias, which are incorporated into an integrated circuit package, allowing for simultaneous fabrication with improved thermal dissipation and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple electronic components are integrated with shrinking feature sizes, then integration density is improved, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent divides the through-via formation process into distinct segments: forming openings through the substrate, selectively filling with conductive material for active vias, and filling with insulating material for dummy vias. This segmentation allows complex multi-material via structures to be manufactured through manageable sequential steps, resolving the contradiction between high integration density and manufacturing complexity
Solution Approach 2:
The patent performs preliminary actions by forming all openings through the substrate before filling, and by applying barrier layers and seed layers in advance of final conductive material deposition. This preliminary structuring simplifies subsequent manufacturing steps while enabling precise control over the final via structures, thereby managing manufacturing complexity at high integration densities
2Reliability
If through vias are formed for electrical connection, then device performance is improved, but thermal dissipation challenges worsen
Solution Approach 1:
The patent applies different materials and structures to different locations: active through vias with conductive material for electrical connection in specific regions, and dummy through vias with insulating material for thermal management in other regions. This local differentiation allows simultaneous optimization of electrical performance and thermal dissipation, resolving the contradiction between electrical connection reliability and thermal management
3Area of stationary object
If heterogeneous dies are integrated with small footprint, then area efficiency is improved, but fabrication yield worsens
Solution Approach 1:
The patent creates a universal via formation process that handles both active electrical connections and dummy thermal/structural features through the same opening formation and selective filling methodology. This universal approach maintains fabrication consistency across heterogeneous die integration, preventing yield degradation despite the complexity of multi-die, multi-function integration in a small footprint
Data Source
AI summary
A method includes: forming first bond pads along a wafer; bonding a first die to a first set of the first bond pads, the first die being electrically connected to the wafer; depositing a gap-fill dielectric over the wafer and around the first die; forming openings in the gap-fill dielectric; forming first active through vias in physical contact with the second set of the first bond pads and first dummy through vias in physical contact with the third set of the first bond pads, the first active through vias being electrically connected to the wafer, the first dummy through vias being electrically isolated from the wafer; forming second bond pads along the first die, the first active through vias, and the first dummy through vias; and bonding a second die to the first die and to a first active via of the first active through vias.